coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: amdfwtool: Change the name of macros for 'BHD'
by Bao Zheng (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Zheng Bao, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55411 to look at the new patch set (#28). Change subject: amdfwtool: Change the name of macros for 'BHD' ...................................................................... amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/psp_verstage/include/psp_verstage.h M src/soc/amd/common/psp_verstage/psp_verstage.c M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 4 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/55411/28 -- To view, visit https://review.coreboot.org/c/coreboot/+/55411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Gerrit-Change-Number: 55411 Gerrit-PatchSet: 28 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Add Dasharo to after-market firmware list
by Igor Bagnucki (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Michał Żygowski, Patrick Georgi, Paul Menzel, Piotr Król. Igor Bagnucki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63396 ) Change subject: Documentation: Add Dasharo to after-market firmware list ...................................................................... Patch Set 5: (1 comment) File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/63396/comment/1b04a929_233d03cc PS4, Line 60: open source > I think in [1], “open-source based” was suggested. […] I have changed the description to include "open-source based" term. Hope, that this discussion can be resolved now. -- To view, visit https://review.coreboot.org/c/coreboot/+/63396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d Gerrit-Change-Number: 63396 Gerrit-PatchSet: 5 Gerrit-Owner: Igor Bagnucki Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 07:10:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add Dasharo to after-market firmware list
by Igor Bagnucki (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Michał Żygowski, Patrick Georgi, Igor Bagnucki, Piotr Król. Hello build bot (Jenkins), Patrick Georgi, Michał Żygowski, Igor Bagnucki, Paul Menzel, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63396 to look at the new patch set (#5). Change subject: Documentation: Add Dasharo to after-market firmware list ...................................................................... Documentation: Add Dasharo to after-market firmware list Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> --- M Documentation/distributions.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/63396/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19dbf70bc9ceec1408944c4029db6eabd5e2254d Gerrit-Change-Number: 63396 Gerrit-PatchSet: 5 Gerrit-Owner: Igor Bagnucki Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Igor Bagnucki Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Add NovaCustom laptops to ships-with-coreboot hw list
by Igor Bagnucki (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Michał Żygowski, Patrick Georgi, Igor Bagnucki, Paul Menzel, Piotr Król. Igor Bagnucki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63389 ) Change subject: Documentation: Add NovaCustom laptops to ships-with-coreboot hw list ...................................................................... Patch Set 3: (1 comment) File Documentation/distributions.md: https://review.coreboot.org/c/coreboot/+/63389/comment/bfa6a954_36712a0f PS2, Line 15: Windows > Microsoft Windows Fixed that -- To view, visit https://review.coreboot.org/c/coreboot/+/63389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0fc521d13362b2f3047eb91af8d5b3ac74eaa1d Gerrit-Change-Number: 63389 Gerrit-PatchSet: 3 Gerrit-Owner: Igor Bagnucki Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 07:06:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Add NovaCustom laptops to ships-with-coreboot hw list
by Igor Bagnucki (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Michał Żygowski, Patrick Georgi, Igor Bagnucki, Piotr Król. Hello build bot (Jenkins), Maciej Pijanowski, Michał Żygowski, Patrick Georgi, Igor Bagnucki, Paul Menzel, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63389 to look at the new patch set (#3). Change subject: Documentation: Add NovaCustom laptops to ships-with-coreboot hw list ...................................................................... Documentation: Add NovaCustom laptops to ships-with-coreboot hw list Change-Id: Ic0fc521d13362b2f3047eb91af8d5b3ac74eaa1d Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> --- M Documentation/distributions.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63389/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0fc521d13362b2f3047eb91af8d5b3ac74eaa1d Gerrit-Change-Number: 63389 Gerrit-PatchSet: 3 Gerrit-Owner: Igor Bagnucki Gerrit-Reviewer: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com> Gerrit-Attention: Igor Bagnucki Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/osiris: Generate SPD ID for supported parts
by David Wu (Code Review) 19 Apr '22

19 Apr '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63706 ) Change subject: mb/google/brya/var/osiris: Generate SPD ID for supported parts ...................................................................... mb/google/brya/var/osiris: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B (Micron) MT53E1G32D2NP-046 WT:B (Micron) H54G46CYRBX267 (Hynix) H54G56CYRBX247 (Hynix) K4U6E3S4AB-MGCL (Samsung) K4UBE3D4AB-MGCL (Samsung) BUG=None TEST=build pass Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 --- M src/mainboard/google/brya/variants/osiris/memory/Makefile.inc M src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt 3 files changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63706/1 diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc index eace2e4..eb91988 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -1,5 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/osiris/memory/ src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt index fa24790..1135950 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -1 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/osiris/memory/ src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT53E512M32D1NP-046 WT:B 0 (0000) +MT53E1G32D2NP-046 WT:B 1 (0001) +H54G46CYRBX267 0 (0000) +H54G56CYRBX247 1 (0001) +K4U6E3S4AB-MGCL 0 (0000) +K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt index 9621137..a188982 100644 --- a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -1,11 +1,6 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B +H54G46CYRBX267 +H54G56CYRBX247 +K4U6E3S4AB-MGCL +K4UBE3D4AB-MGCL -- To view, visit https://review.coreboot.org/c/coreboot/+/63706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Gerrit-Change-Number: 63706 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
by Meera Ravindranath (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Daniil Lunev, Subrata Banik, Wonkyu Kim, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, Gwendal Grignou. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: Requesting review here. -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Daniil Lunev <dlunev(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 06:22:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Varshit B Pandya (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar. Varshit B Pandya has removed Subrata Banik from this change. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... Removed reviewer Subrata Banik. -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to set SPI controller VCL
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63626 ) Change subject: soc/intel/cmn/fast_spi: Add API to set SPI controller VCL ...................................................................... soc/intel/cmn/fast_spi: Add API to set SPI controller VCL This patch creates a helper function to set SPI controller VCL bit as recommended by Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified that SPI flash controller MMIO register 0xC4 bit 30 is set. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_def.h M src/soc/intel/common/block/include/intelblocks/fast_spi.h 3 files changed, 28 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 4ff1e9b..7e8a1a2 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -171,6 +171,23 @@ } /* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void) +{ + void *spibar = fast_spi_get_bar(); + + /* + * SPI Flash Programming Guide Section 5.5.2 describes Vendor Component Lock (VCL). + * It is recommended to set the VCL bit. VCL applies to both VSCC0 and VSCC1. + * Without this bit being set, it is possible to modify Host/GbE VSCC register(s), + * which might results in undesired host and integrated GbE Serial Flash + * functionality. + */ + setbits32(spibar + SPIBAR_SFDP0_VSCC0, SPIBAR_VSCC0_VCL); +} + +/* * Set FAST_SPIBAR Soft Reset Data Register value. */ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data) diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index f28865d..0be3dcd 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -131,6 +131,13 @@ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +/* + * Register Offset of BIOS Vendor Specific Component Capabilities (VSCC) + * for Component 0 Register + */ +#define SPIBAR_SFDP0_VSCC0 0xc4 +#define SPIBAR_VSCC0_VCL (1 << 30) + /* Bit definitions for PTINX (0xcc) register */ #define SPIBAR_PTINX_COMP_0 (0 << 14) #define SPIBAR_PTINX_COMP_1 (1 << 14) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 1e96603..90f1cb2 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -43,6 +43,10 @@ */ void fast_spi_pr_dlock(void); /* + * Set FAST_SPIBAR + VSCC0 (0xC4) register VCL (bit 30). + */ +void fast_spi_vscc0_lock(void); +/* * Set FAST_SPIBAR Soft Reset Data Register value. */ void fast_spi_set_strap_msg_data(uint32_t soft_reset_data); -- To view, visit https://review.coreboot.org/c/coreboot/+/63626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9a12db1bab81779fd8e7db90221d08da3c65011 Gerrit-Change-Number: 63626 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63625 ) Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status ...................................................................... soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status This patch creates a helper function to clear HSFSTS_CTL (offset 0x04) register Bits 0 to 4. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to clear all SPI outstanding status before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63625 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3..4ff1e9b 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -428,3 +428,11 @@ bios_cntl |= SPI_BIOS_CONTROL_WPD; pci_write_config8(dev, SPI_BIOS_CONTROL, bios_cntl); } + +void fast_spi_clear_outstanding_status(void) +{ + void *spibar = fast_spi_get_bar(); + + /* Make sure all W1C status bits get cleared. */ + write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); +} diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index eb3f2aa..1e96603 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -5,6 +5,8 @@ #include <types.h> +/* Clear any SPI outstanding status bits, i.e., FCERR, FDONE etc. */ +void fast_spi_clear_outstanding_status(void); /* Check if SPI transaction is pending */ int fast_spi_cycle_in_progress(void); /* 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Gerrit-Change-Number: 63625 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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