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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63589
to look at the new patch set (#3).
Change subject: soc/amd/common/block/cpu/*: Make ucode update more generic
......................................................................
soc/amd/common/block/cpu/*: Make ucode update more generic
Use the equivalent cpuid in the microcode header to name the update file
in cbfs. This allows the SOC to directly locate its microcode file when
there are multiple processor revisions.
TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode
files and booted. Verified that only the sabrina microcode file was
successfully loaded
Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/common/block/cpu/Kconfig
M src/soc/amd/common/block/cpu/Makefile.inc
M src/soc/amd/common/block/cpu/update_microcode.c
M src/soc/amd/picasso/Makefile.inc
M src/soc/amd/sabrina/Makefile.inc
6 files changed, 47 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63589/3
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63703 )
Change subject: soc/amd/sabrina: Disable lpc ldrq function
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/sabrina/include/soc/espi.h:
https://review.coreboot.org/c/coreboot/+/63703/comment/59e8e2c2_3ce2aef6
PS1, Line 6: define
Why move them? We don't need to make them public for others to consume.
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/4574ee5d_724c7817
PS4, Line 37: SMI handler
> > > > > > Sorry, thinking error on my part. […]
This is intended to be a temporary workaround until we have a permanent solution/workaround from Intel. We suspect the permanent solution will end up in the ADL-P chipset blob collateral (i.e. not FSP), but don't know for sure yet, and this should be able to be reverted later.
_PTS may work, would have to test that there are no additional operations that happen after that runs to change the IP state again.
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63707 )
Change subject: vendorcode/intel/fsp: Update FSP header file for Alder Lake N FSP v3133.00
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63707/comment/69420a43_6060add3
PS1, Line 9: The headers added are generated as per FSP v3133.00
: Previous FSP version was v3054.02
: Changes Include:
> Sure, resolved with dot in end of sentences.
No, please fully read my comment. Please format it like:
```
vc/intel/fsp: alderlake_n: Update FSP header file from v3054.02 to v3133.00
The headers added are generated as per FSP v3133.00. Previous FSP
version was v3054.02.
Changes include:
- UPD Enable eMMC Controller Offset removed in FspsUpd.h
- UPD UnusedUpdSpace name update in FspmUpd.h
```
Patchset:
PS3:
As author, you do not need to score your own change-sets.
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Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63424 )
Change subject: tpm: Refactor TPM Kconfig dimensions
......................................................................
Patch Set 16:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63424/comment/4b375c8f_81217f5b
PS13, Line 7: Kconfig
> Well, the change isn't solely about Kconfig anymore, but also touches code. […]
Yes, I feel that the changes required to introduce chip.c files are balooning, and Jenkins is currently showing many linker errors. I need to land this refactoring (accepting new Ti50 identification), before I can land the Ti50 change to start presenting the new identification, and I want to do the latter before an upcoming FSI of Ti50 firmware.
I think I am going to split this CL into a pure Kconfig refactoring, and then another CL that introduces chip.c files, and rectifies the conditions under which that code is compiled and linked. Stay tuned.
File src/drivers/crb/chip.c:
https://review.coreboot.org/c/coreboot/+/63424/comment/114383e7_91c268a0
PS13, Line 17: .acpi_fill_ssdt = crb_tpm_fill_ssdt,
> The definitions of these two functions need to move into this file too, otherwise you have missing r […]
Done
File src/drivers/pc80/tpm/chip.c:
https://review.coreboot.org/c/coreboot/+/63424/comment/62e353b6_85482e14
PS13, Line 14: u8 value = read8(TIS_REG(locality, TIS_REG_INT_VECTOR));
> Jenkins complains that you don't have TIS_REG() in this context. […]
Many of these small inline functions are being used both from the methods now in the new chip.c file, as well as methods remaining in tis.c. I have created a new tis.h to contain shared macros and inline function definitions.
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Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 19:
(1 comment)
Patchset:
PS9:
> As far as I'm aware this is their current draft patch: CB:57615. Does someone who understands PCIe better than I do follow what's going on there
It really seems to be just a draft. I doubt this code works (it's more
than just whitespace errors). It's not safe to derive anything about the
hardware from that code. Is there public QC documentation by now? If not,
I suggest to make it a requirement before they waste another 6 months ;)
> (is it really normal to run that much code for each register access)?
No, and it's not necessary for every access in this case. If you look at
the mapping, it doesn't change unless the accessed device/function changes.
So one could at least cache the function used and only re-run the mapping
procedure if that changes (the same applies to Mediatek btw. but as it's
a single MMIO write to change the mapping, probably not worth it).
Oh, the respective coreboot code looks different, it restores another
mapping after every access. So something is fishy...
Another thing I've noticed: in Linux, the root bus is treated very
differently. After all, it looks like tested code, i.e. code that
was tested for one specific setup and not written for PCIe in general.
> Also, as far as I can see the mmio_size is set to 1MB in CB:61773, so I guess it's not always 4K?
It's hard to tell if this is a hardware limit or a choice made for coreboot
that could change and should be passed via cbtables. AFAICS, the libpayload
code only makes use of 4K. However, the bus/device/function is encoded from
bit 16 up, so that _might_ suggest the mapping requires 64K per function.
If it's freely configurable, I guess one could map enough to cover all buses
like ECAM? (if the CPU side supports enough physical address bits)
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Change subject: soc/amd/non_car/memlayout_x86.ld: Top align the bootblock
......................................................................
Patch Set 11: Code-Review-1
(1 comment)
Patchset:
PS11:
Does this even make sense? The PSP loads in RAM regardless. There is likely little benefit to have it optimized like this.
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Ferass ELÂ HAFIDI has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 )
Change subject: apple/macbook21: configure the clockgen and add C3 CPU state
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/1b49b732_7b5c6061
PS4, Line 34: .latency = 17,
> > I guess it would be safe to just set that value to 1. Thoughts? […]
That sounds like a good idea too.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63587 )
Change subject: apple/macbook21: configure the clockgen and add C3 CPU state
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/5dd8f11b_17c0e4be
PS4, Line 34: .latency = 17,
> I guess it would be safe to just set that value to 1. Thoughts?
I'd just leave it at what the vendor set.
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