coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/brya0: configure gpio for headset
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Amanda Hwang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63721 ) Change subject: mb/google/brya/var/brya0: configure gpio for headset ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Will this have any negative effects on earlier boards without the headset functionality? -- To view, visit https://review.coreboot.org/c/coreboot/+/63721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93070a8096d43557a50e5a545227f2906e299d8e Gerrit-Change-Number: 63721 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 20:06:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GPU power sequencing
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Angel Pons, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62384 ) Change subject: mb/google/brya/var/agah: Add GPU power sequencing ...................................................................... Patch Set 3: (12 comments) Patchset: PS3: Thanks Angel! 😊 File src/mainboard/google/brya/variants/agah/variant.c: https://review.coreboot.org/c/coreboot/+/62384/comment/ac846f8d_384fdba2 PS3, Line 34: gpio_t pg_gpio; > AIUI, `pwr_en_gpio` is an output (wired to the VR's "enable" pin) and `pg_gpio` is an input (wired f […] You got it! I can add comments. https://review.coreboot.org/c/coreboot/+/62384/comment/67aa2dce_48b21d5f PS3, Line 56: timeout_us > Shouldn't this be `seq->timeout_us`? The `timeout_us` parameter is always `DEFAULT_PG_TIMEOUT_US`, a […] Oops, yes. https://review.coreboot.org/c/coreboot/+/62384/comment/d156ac3a_4a88e22d PS3, Line 65: gpio_output(GPU_ALLRAILS_PG, 0); > Unlike the other power-good signals, this one is an output. […] Yes https://review.coreboot.org/c/coreboot/+/62384/comment/a06bba9a_544689bc PS3, Line 77: a > nit: capitalize `A` Done https://review.coreboot.org/c/coreboot/+/62384/comment/1a062cd6_13973141 PS3, Line 85: the series > What does this mean? Good question 😂 fixed https://review.coreboot.org/c/coreboot/+/62384/comment/fcdbfba8_398d43c2 PS3, Line 126: void variant_fill_ssdt(const struct device *dev) > Does this need to be skipped if `gpu_powered_on` is false? Good call, it would not have enumerated in that case! 😊 https://review.coreboot.org/c/coreboot/+/62384/comment/e3d0c751_18a1d239 PS3, Line 126: dev > I'm pretty sure this `dev` is unused, as it's the mainboard device. […] 👍 good idea https://review.coreboot.org/c/coreboot/+/62384/comment/10e53d6a_3d412de9 PS3, Line 145: 4 > nit: sizeof(uint32_t) Done https://review.coreboot.org/c/coreboot/+/62384/comment/23da1cdc_ff02602c PS3, Line 149: res = probe_resource(dgpu, idx); > Does this work for 64-bit resources? In a way, yes... in PCI land there are BAR0-BAR5, each 32 bits wide, but a 64-bit BAR is made from combining two 32-bit BARs together (e.g. BAR0-BAR1) IIRC, and this (should) correctly copy those 6 BAR registers into place. https://review.coreboot.org/c/coreboot/+/62384/comment/1167edb2_991d4a01 PS3, Line 154: PCI_BASE_ADDRESS_0 - : VGAB_BYTE_OFFSET + sizeof(uint32_t) * i > Isn't this equivalent to `idx - VGAB_BYTE_OFFSET`? Good eye! That reads much cleaner https://review.coreboot.org/c/coreboot/+/62384/comment/9fe048ac_42a9843c PS3, Line 160: */ > nit: space before comment end Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Gerrit-Change-Number: 62384 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 20:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GPU power sequencing
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Angel Pons, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62384 to look at the new patch set (#4). Change subject: mb/google/brya/var/agah: Add GPU power sequencing ...................................................................... mb/google/brya/var/agah: Add GPU power sequencing This patch adds support for power sequencing of the Nvidia GN3050 for agah, which uses PCH GPIOs to control the 5 power rails required for the GPU. The GPU is power sequenced on during mainboard initialization, then it is enumerated on the PCI bus and its resources are assigned. This GPU will be used in a sort of "hybrid graphics" mode, therefore during finalization, since its PCI BARs are saved into ACPI memory and the GPU is not required upon initial boot, the GPU is power sequenced off. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 --- M src/mainboard/google/brya/variants/agah/Makefile.inc M src/mainboard/google/brya/variants/agah/overridetree.cb A src/mainboard/google/brya/variants/agah/variant.c 3 files changed, 194 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62384/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Gerrit-Change-Number: 62384 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/cpu/*: Make ucode update more generic
by Raul Rangel (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Angel Pons, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/cpu/*: Make ucode update more generic ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/63589/comment/a1934bbc_e9aef583 PS2, Line 79: for > For picasso soc, each microcode variant will be in its own file (cpu_microcode_8180. […] Can you point me to the CLs? -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 19 Apr 2022 20:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/corta: limit dram speed at 4800
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Scott Chao, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63682 ) Change subject: mb/google/brya/var/corta: limit dram speed at 4800 ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63682/comment/909fe930_b9c2cc36 PS3, Line 9: For tyep-3 PCB board suggestion: ``` When using LPDDR5 on a Type-C PCB, the Intel PDG recommends a maximum DRAM speed of 4800 MT/s. ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:47:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Paul Menzel, Robert Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63440 ) Change subject: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6% ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:44:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/cpu/*: Make ucode update more generic
by Fred Reitberger (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/cpu/*: Make ucode update more generic ...................................................................... Patch Set 3: (4 comments) File src/soc/amd/common/block/cpu/update_microcode.c: https://review.coreboot.org/c/coreboot/+/63589/comment/0a2823d3_d0cc3400 PS2, Line 79: for > So you are dropping the for loop.... We need that for the zork/picasso/dali platforms. […] For picasso soc, each microcode variant will be in its own file (cpu_microcode_8180.bin, cpu_microcode_8181.bin, and cpu_microcode_8201.bin). There are no longer multiple microcodes in a single file, so the for loop is not needed anymore. On a given variant (8180, 8181, or 8201), it will only look up its own microcode. https://review.coreboot.org/c/coreboot/+/63589/comment/9eeb9cf3_59b23d41 PS2, Line 66: static const struct microcode *find_microcode(const struct microcode *ucode, uint16_t equivalent_processor_rev_id) > clang-format Done https://review.coreboot.org/c/coreboot/+/63589/comment/0b22f964_f1dc749b PS2, Line 83: 23 > Do you need the size? Tested a timeless build with and without the size, and they were identical. Good catch, size was not needed https://review.coreboot.org/c/coreboot/+/63589/comment/2b3bcc69_1ecaa5f2 PS2, Line 86: snprintf > I would check the return code. Leaving unresolved for now - I moved the code into the !cache_valid block so it only runs once. If snprintf were to fail (it really should not here), then the cbfs_map would fail and printk below should catch it and print what happened. Same thing in the preload_microcode() function below. I'm not sure what is gained by checking the return value here. I used https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… as a reference to load a file from CBFS based on an ID in the file name. -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:42:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/corta: modify DQ/ DQS table
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Scott Chao, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63681 ) Change subject: mb/google/brya/var/corta: modify DQ/ DQS table ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS4: > @Tim, I think we don't need the DQ map still can PASS the MRC training. As our per experiment. It might be required for LP5? -- To view, visit https://review.coreboot.org/c/coreboot/+/63681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6acf8cb9474f816374743fd1e800da46958993d Gerrit-Change-Number: 63681 Gerrit-PatchSet: 5 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63561 ) Change subject: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/63561/comment/67941d5f_a2e53ddd PS1, Line 431: if (segments->len != 0) > how about keeping it as BIOS_ERR for segments->len > 0, but setting it to BIOS_SPEW for len = 0? 👍 maybe break out the `segments->len == 0` case into a boolean variable? -- To view, visit https://review.coreboot.org/c/coreboot/+/63561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518e849f4c476c264a1464886b1853af66c0b29d Gerrit-Change-Number: 63561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:33:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Tim Wawrzynczak (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Frank Wu, Eric Lai, Amanda Hwang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 19:31:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022