coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/intel/alderlake: Implement PMC static function lock
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63689 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Implement PMC static function lock ...................................................................... soc/intel/alderlake: Implement PMC static function lock This patch performs PMC static function lockdown. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified PMC static PG lock (bit 31) is set. > iotools mmio_read32 0xfe001e20 0x80000000 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 --- M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/lockdown.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63689/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 Gerrit-Change-Number: 63689 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63737 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function ...................................................................... soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function This patch refactors the `pmc_lockdown_cfg()` to remove the helper functions and uses the `setbits32` function to enforce bit locking as applicable. BUG=b:211954778 TEST=Able to build google/redrix with these changes and boot to OS. > localhost ~ # iotools mmio_read32 0xfe0018c4 0x85000000 (bit 31 is set) > localhost ~ # iotools mmio_read32 0xfe001024 0x00062610 (bits 4, 17 and 18 are set) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 5 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/63737/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Gerrit-Change-Number: 63737 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: cpu/intel/haswell/smm: Set code check bit
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63788 ) Change subject: cpu/intel/haswell/smm: Set code check bit ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/haswell/haswell.h: https://review.coreboot.org/c/coreboot/+/63788/comment/aa5b6ce4_d480fd20 PS1, Line 63: defien spelling -- To view, visit https://review.coreboot.org/c/coreboot/+/63788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254fb348483d2873917cf8c94c8b60e6f2d2c4e7 Gerrit-Change-Number: 63788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 22 Apr 2022 13:29:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/haswell/smm: Set code check bit
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63788 ) Change subject: cpu/intel/haswell/smm: Set code check bit ...................................................................... cpu/intel/haswell/smm: Set code check bit This makes sure that only code in TSEG gets executed. See section 34.17.1 "SMM Handler Code Access Control" in the 'Intel 64 and IA-32 Architectures Software Developer’s Manual' Change-Id: I254fb348483d2873917cf8c94c8b60e6f2d2c4e7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/haswell/finalize.c M src/cpu/intel/haswell/haswell.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63788/1 diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index 3983876..5635bc1 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -9,4 +9,10 @@ { /* Lock memory configuration to protect SMM */ msr_set(MSR_LT_LOCK_MEMORY, BIT(0)); + + const msr_t smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR); + if (smm_mca_cap.hi & SMM_CODE_ACESSS_CHK_MASK) { + msr_t smm_feature = rdmsr(SMM_FEATURE_CONTROL_MSR); + smm_feature.lo |= SMM_CODE_CHK_EN | SMM_FEATURE_CONTROL_LOCK; + } } diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 133a129..b316032 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -44,6 +44,8 @@ #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define SMM_CODE_ACCESS_CHK_BIT 58 +#define SMM_CODE_ACESSS_CHK_MASK (1 << (SMM_CODE_ACCESS_CHK_BIT - 32)) #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) @@ -58,7 +60,9 @@ #define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define SMM_FEATURE_CONTROL_MSR 0x4e0 +#defien SMM_FEATURE_CONTROL_LOCK (1 << 0) #define SMM_CPU_SAVE_EN (1 << 1) +#define SMM_CODE_CHK_EN (1 << 2) #define MSR_C_STATE_LATENCY_CONTROL_0 0x60a #define MSR_C_STATE_LATENCY_CONTROL_1 0x60b -- To view, visit https://review.coreboot.org/c/coreboot/+/63788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I254fb348483d2873917cf8c94c8b60e6f2d2c4e7 Gerrit-Change-Number: 63788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/google/chromeec: Add empty string check for OEM string
by Henry Sun (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Kangheui Won, Tim Wawrzynczak, Eric Lai. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63772 ) Change subject: ec/google/chromeec: Add empty string check for OEM string ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: LGTM, thank you Eric for fixing this. -- To view, visit https://review.coreboot.org/c/coreboot/+/63772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82 Gerrit-Change-Number: 63772 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 12:53:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63737 ) Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/alderlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/63737/comment/066e5486_903acbcf PS2, Line 18: pmc_mmio_regs() nit: you could store the address in a local variable, like the individual functions did (but this time there's just one variable). WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/63737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Gerrit-Change-Number: 63737 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 12:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/ehl: Remove PSE init 'magic code'
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Praveen HP, Mario Scheithauer, Lean Sheng Tan, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63775 ) Change subject: soc/intel/ehl: Remove PSE init 'magic code' ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > I wouldn't be too fast here. […] Good point. If so, then I'd suggest introducing a Kconfig option so that this magic is only performed when using the Intel blob. -- To view, visit https://review.coreboot.org/c/coreboot/+/63775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cfacac62cae0a234e4c4927454311454ab01bdd Gerrit-Change-Number: 63775 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 12:51:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities
by Michał Żygowski (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63787 ) Change subject: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities ...................................................................... soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0bb5a5d7732c16074c5d517ac21e24de9a898403 --- M src/soc/intel/alderlake/acpi/gpio.asl 1 file changed, 15 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63787/1 diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index d273625..7b37995 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -16,6 +16,8 @@ { Memory32Fixed (ReadWrite, 0, 0, COM0) Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) Memory32Fixed (ReadWrite, 0, 0, COM4) Memory32Fixed (ReadWrite, 0, 0, COM5) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) @@ -35,6 +37,18 @@ BAS1 = ^^PCRB (PID_GPIOCOM1) LEN1 = GPIO_BASE_SIZE + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE + /* GPIO Community 4 */ CreateDWordField (^RBUF, ^COM4._BAS, BAS4) CreateDWordField (^RBUF, ^COM4._LEN, LEN4) @@ -121,7 +135,7 @@ Case (COMM_2) { Local0 = PID_GPIOCOM2 } - case (COMM_3) { + Case (COMM_3) { Local0 = PID_GPIOCOM3 } Case (COMM_4) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb5a5d7732c16074c5d517ac21e24de9a898403 Gerrit-Change-Number: 63787 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: intelblocks/cnvi: Add ADL-S CNVi WiFi device IDs
by Michał Żygowski (Code Review) 22 Apr '22

22 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63786 ) Change subject: intelblocks/cnvi: Add ADL-S CNVi WiFi device IDs ...................................................................... intelblocks/cnvi: Add ADL-S CNVi WiFi device IDs Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifd4814c7ec0b3b0b152efebb4036536f8c647be7 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63786/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7c460f9..f994043 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4414,6 +4414,10 @@ #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_1 0x54f1 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_2 0x54f2 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_3 0x54f3 +#define PCI_DID_INTEL_ADL_S_CNVI_WIFI_0 0x7af0 +#define PCI_DID_INTEL_ADL_S_CNVI_WIFI_1 0x7af1 +#define PCI_DID_INTEL_ADL_S_CNVI_WIFI_2 0x7af2 +#define PCI_DID_INTEL_ADL_S_CNVI_WIFI_3 0x7af3 #define PCI_DID_INTEL_MTL_CNVI_WIFI_0 0x7e40 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c index f4fa019..8109ec4 100644 --- a/src/soc/intel/common/block/cnvi/cnvi.c +++ b/src/soc/intel/common/block/cnvi/cnvi.c @@ -47,6 +47,10 @@ PCI_DID_INTEL_ADL_N_CNVI_WIFI_1, PCI_DID_INTEL_ADL_N_CNVI_WIFI_2, PCI_DID_INTEL_ADL_N_CNVI_WIFI_3, + PCI_DID_INTEL_ADL_S_CNVI_WIFI_0, + PCI_DID_INTEL_ADL_S_CNVI_WIFI_1, + PCI_DID_INTEL_ADL_S_CNVI_WIFI_2, + PCI_DID_INTEL_ADL_S_CNVI_WIFI_3, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63786 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd4814c7ec0b3b0b152efebb4036536f8c647be7 Gerrit-Change-Number: 63786 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/alderlake/acpi: Add ADL-S devices
by Michał Żygowski (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63785 ) Change subject: soc/intel/alderlake/acpi: Add ADL-S devices ...................................................................... soc/intel/alderlake/acpi: Add ADL-S devices Add PCIe Root Ports, USB ports, GPIO Controller and SIO devices for ADL-S chipset. Add IRQ routing tables for PCIe Root ports up to 28th. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c --- A src/soc/intel/alderlake/acpi/gpio_pch_s.asl M src/soc/intel/alderlake/acpi/pcie.asl M src/soc/intel/alderlake/acpi/serialio.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/alderlake/acpi/xhci.asl 5 files changed, 492 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63785/1 diff --git a/src/soc/intel/alderlake/acpi/gpio_pch_s.asl b/src/soc/intel/alderlake/acpi/gpio_pch_s.asl new file mode 100644 index 0000000..f6a3226 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/gpio_pch_s.asl @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <intelblocks/gpio.h> +#include <soc/gpio_defs_pch_s.h> +#include <soc/intel/common/acpi/gpio.asl> +#include <soc/intel/common/block/acpi/acpi/gpio_op.asl> +#include <soc/irq.h> +#include <soc/pcr_ids.h> + +Device (GPIO) +{ + Name (_HID, CROS_GPIO_NAME) + Name (_UID, 0) + Name (_DDN, "GPIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, COM0) + Memory32Fixed (ReadWrite, 0, 0, COM1) + Memory32Fixed (ReadWrite, 0, 0, COM2) + Memory32Fixed (ReadWrite, 0, 0, COM3) + Memory32Fixed (ReadWrite, 0, 0, COM4) + Memory32Fixed (ReadWrite, 0, 0, COM5) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ) + { GPIO_IRQ14 } + }) + Method (_CRS, 0, NotSerialized) + { + /* GPIO Community 0 */ + CreateDWordField (^RBUF, ^COM0._BAS, BAS0) + CreateDWordField (^RBUF, ^COM0._LEN, LEN0) + BAS0 = ^^PCRB (PID_GPIOCOM0) + LEN0 = GPIO_BASE_SIZE + + /* GPIO Community 1 */ + CreateDWordField (^RBUF, ^COM1._BAS, BAS1) + CreateDWordField (^RBUF, ^COM1._LEN, LEN1) + BAS1 = ^^PCRB (PID_GPIOCOM1) + LEN1 = GPIO_BASE_SIZE + + /* GPIO Community 2 */ + CreateDWordField (^RBUF, ^COM2._BAS, BAS2) + CreateDWordField (^RBUF, ^COM2._LEN, LEN2) + BAS2 = ^^PCRB (PID_GPIOCOM2) + LEN2 = GPIO_BASE_SIZE + + /* GPIO Community 3 */ + CreateDWordField (^RBUF, ^COM3._BAS, BAS3) + CreateDWordField (^RBUF, ^COM3._LEN, LEN3) + BAS3 = ^^PCRB (PID_GPIOCOM3) + LEN3 = GPIO_BASE_SIZE + + /* GPIO Community 4 */ + CreateDWordField (^RBUF, ^COM4._BAS, BAS4) + CreateDWordField (^RBUF, ^COM4._LEN, LEN4) + BAS4 = ^^PCRB (PID_GPIOCOM4) + LEN4 = GPIO_BASE_SIZE + + /* GPIO Community 5 */ + CreateDWordField (^RBUF, ^COM5._BAS, BAS5) + CreateDWordField (^RBUF, ^COM5._LEN, LEN5) + BAS5 = ^^PCRB (PID_GPIOCOM5) + LEN5 = GPIO_BASE_SIZE + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } +} + +/* + * Get GPIO DW0 Address + * Arg0 - GPIO Number + */ +Method (GADD, 1, NotSerialized) +{ + /* GPIO Community 0 */ + If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END) + { + Local0 = PID_GPIOCOM0 + Local1 = Arg0 - GPIO_COM0_START + } + /* GPIO Community 1 */ + If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END) + { + Local0 = PID_GPIOCOM1 + Local1 = Arg0 - GPIO_COM1_START + } + /* GPIO Community 2 */ + If (Arg0 >= GPIO_COM2_START && Arg0 <= GPIO_COM2_END) + { + Local0 = PID_GPIOCOM2 + Local1 = Arg0 - GPIO_COM2_START + } + /* GPIO Community 3 */ + If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END) + { + Local0 = PID_GPIOCOM3 + Local1 = Arg0 - GPIO_COM3_START + } + /* GPIO Community 4 */ + If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END) + { + Local0 = PID_GPIOCOM4 + Local1 = Arg0 - GPIO_COM4_START + } + /* GPIO Community 05*/ + If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END) + { + Local0 = PID_GPIOCOM5 + Local1 = Arg0 - GPIO_COM5_START + } + + Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16) + Return (Local2) +} + +/* + * Return PCR Port ID of GPIO Communities + * + * Arg0: GPIO Community (0-5) + */ +Method (GPID, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (COMM_0) { + Local0 = PID_GPIOCOM0 + } + Case (COMM_1) { + Local0 = PID_GPIOCOM1 + } + Case (COMM_2) { + Local0 = PID_GPIOCOM2 + } + Case (COMM_3) { + Local0 = PID_GPIOCOM3 + } + Case (COMM_4) { + Local0 = PID_GPIOCOM4 + } + Case (COMM_5) { + Local0 = PID_GPIOCOM5 + } + Default { + Return (0) + } + } + + Return (Local0) +} diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index f2123aa..201da05 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -54,7 +54,7 @@ Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9, 13 }) { + Case (Package () { 1, 5, 9, 13, 17, 21, 25 }) { If (PICM) { Return (IQAA) } Else { @@ -62,7 +62,7 @@ } } - Case (Package () { 2, 6, 10, 14 }) { + Case (Package () { 2, 6, 10, 14, 18, 22, 26 }) { If (PICM) { Return (IQBA) } Else { @@ -70,7 +70,7 @@ } } - Case (Package () { 3, 7, 11, 15 }) { + Case (Package () { 3, 7, 11, 15, 19, 23, 27 }) { If (PICM) { Return (IQCA) } Else { @@ -78,7 +78,7 @@ } } - Case (Package () { 4, 8, 12, 16 }) { + Case (Package () { 4, 8, 12, 16, 20, 24, 28 }) { If (PICM) { Return (IQDA) } Else { @@ -300,6 +300,296 @@ } } +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP17) +{ + Name (_ADR, 0x001B0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP18) +{ + Name (_ADR, 0x001B0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP19) +{ + Name (_ADR, 0x001B0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP20) +{ + Name (_ADR, 0x001B0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP21) +{ + Name (_ADR, 0x001B0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP22) +{ + Name (_ADR, 0x001B0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP23) +{ + Name (_ADR, 0x001B0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP24) +{ + Name (_ADR, 0x001B0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP25) +{ + Name (_ADR, 0x001A0000) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP26) +{ + Name (_ADR, 0x001A0001) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP27) +{ + Name (_ADR, 0x001A0002) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP28) +{ + Name (_ADR, 0x001A0003) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (PEG0) +{ + Name (_ADR, 0x00060000) +} + +Device (PEG2) +{ + Name (_ADR, 0x00010000) +} + +Device (PEG3) +{ + Name (_ADR, 0x00010001) +} +#endif + + #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) Device (PEG0) { diff --git a/src/soc/intel/alderlake/acpi/serialio.asl b/src/soc/intel/alderlake/acpi/serialio.asl index a325953..93632fc 100644 --- a/src/soc/intel/alderlake/acpi/serialio.asl +++ b/src/soc/intel/alderlake/acpi/serialio.asl @@ -91,3 +91,9 @@ Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") } + +Device (UAR3) +{ + Name (_ADR, 0x00110000) + Name (_DDN, "Serial IO UART Controller 3") +} diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 3c37d57..57fc401 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -12,7 +12,11 @@ #include "camera_clock_ctl.asl" /* GPIO controller */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#include "gpio_pch_s.asl" +#else #include "gpio.asl" +#endif /* ESPI 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index 9c70d3f..34ff612 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -23,7 +23,40 @@ { } +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* Root Hub for Alder Lake-P PCH */ + Device (RHUB) + { + Name (_ADR, Zero) + /* USB2 */ + Device (HS01) { Name (_ADR, 1) } + Device (HS02) { Name (_ADR, 2) } + Device (HS03) { Name (_ADR, 3) } + Device (HS04) { Name (_ADR, 4) } + Device (HS05) { Name (_ADR, 5) } + Device (HS06) { Name (_ADR, 6) } + Device (HS07) { Name (_ADR, 7) } + Device (HS08) { Name (_ADR, 8) } + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + Device (HS13) { Name (_ADR, 13) } + Device (HS14) { Name (_ADR, 14) } + /* USB3 */ + Device (SS01) { Name (_ADR, 15) } + Device (SS02) { Name (_ADR, 16) } + Device (SS03) { Name (_ADR, 17) } + Device (SS04) { Name (_ADR, 18) } + Device (SS05) { Name (_ADR, 19) } + Device (SS06) { Name (_ADR, 20) } + Device (SS07) { Name (_ADR, 21) } + Device (SS08) { Name (_ADR, 22) } + Device (SS09) { Name (_ADR, 23) } + Device (SS10) { Name (_ADR, 24) } + } +#else /* Root Hub for Alder Lake-P PCH */ Device (RHUB) { @@ -46,4 +79,5 @@ Device (SS03) { Name (_ADR, 13) } Device (SS04) { Name (_ADR, 14) } } +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/63785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c Gerrit-Change-Number: 63785 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022