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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61311 )
Change subject: console: Add IO port serial logging
......................................................................
Patch Set 5:
(4 comments)
File src/arch/x86/include/arch/io.h:
https://review.coreboot.org/c/coreboot/+/61311/comment/a3708577_151dc03e
PS5, Line 8: 0x5f535452ul
This is really a SIMNow sentinel value. I don't think it belongs with common arch/io
File src/arch/x86/post.c:
https://review.coreboot.org/c/coreboot/+/61311/comment/7e02c43a_613fd4f2
PS5, Line 10: if (CONFIG(CONSOLE_AMD_IO_PORT))
: outl(AMD_IO_PORT_DATA_END, CONFIG_POST_IO_PORT);
Instead of modifying the common code, can we modify the simnow_tx_byte method to write the BEGIN byte, character byte, then END byte. Sure it will be slow, but simnow is already slow. This will keep the default ioport write working and hide all the simnow complexity.
File src/include/console/io_port.h:
PS5:
Can we rename this to simnow.h?
File src/soc/amd/sabrina/bootblock.c:
https://review.coreboot.org/c/coreboot/+/61311/comment/d2f247af_b5bd4158
PS5, Line 39: if (CONFIG(CONSOLE_AMD_IO_PORT))
: outl(AMD_IO_PORT_DATA_BEGIN, CONFIG_POST_IO_PORT);
This should be done as part of the console_init
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
soc/intel/cmn/lockdown: Perform SA lockdown configuration
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/tigerlake/finalize.c
6 files changed, 13 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63518/11
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Change subject: soc/amd/sabrina/psp_verstage: Add platform_report_boot_mode API
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/sabrina/psp_verstage: Unify SVC ID
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/soc/amd/sabrina/psp_verstage/svc.h:
https://review.coreboot.org/c/coreboot/+/63729/comment/f2c94fe0_3079c782
PS1, Line 144:
> Not in the first set of sub-commands being supported. […]
Ack
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Michał Żygowski has uploaded a new patch set (#12) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/63499 )
Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree
......................................................................
mb/msi/ms7d25: add basic FSP configuration in devicetree
Configure some basic FSP parameters in devicetree for
to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/msi/ms7d25/devicetree.cb
1 file changed, 72 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/12
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63518
to look at the new patch set (#10).
Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
soc/intel/cmn/lockdown: Perform SA lockdown configuration
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/tigerlake/finalize.c
6 files changed, 10 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63518/10
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Change subject: cpu/intel/*: Set SMM SMRR code access check bit
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Interesting. Xeon-SP has PCI addresses for that instead of MSR. Maybe it's to support multiple packages at once? Need to investigate.
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