coreboot-gerrit April 2022

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Change in coreboot[master]: console: Add IO port serial logging
by Alexey Buyanov (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Nico Huber, Marshall Dawson, Paul Menzel, Julius Werner, Nikolai Vyssotski, Fred Reitberger, Felix Held. Alexey Buyanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61311 ) Change subject: console: Add IO port serial logging ...................................................................... Patch Set 5: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61311/comment/d9fdf710_dbdcf418 PS4, Line 9: IO ports can be used for debug data output as an : alternative for UART. Protocols used to output this data can : vary. The patch ports a custom version of such a protocol to : coreboot debug log printing routines. : Use cases may include UART problems bypassing or using of systems : without UART. > Thank you, will do. Done https://review.coreboot.org/c/coreboot/+/61311/comment/0ed2a1f2_d41805b6 PS4, Line 15: > Hi, Paul, this was tested by receiving data through port 80 and then interpreting it as per the prot […] Done Patchset: PS5: Hello, please see my responds below and let me know if they are reasonable. Thanks, Alex. File src/arch/x86/include/arch/io.h: https://review.coreboot.org/c/coreboot/+/61311/comment/fc9434d2_efcefd42 PS5, Line 8: 0x5f535452ul > This is really a SIMNow sentinel value. […] Ack File src/arch/x86/post.c: https://review.coreboot.org/c/coreboot/+/61311/comment/459e3675_27036252 PS5, Line 10: if (CONFIG(CONSOLE_AMD_IO_PORT)) : outl(AMD_IO_PORT_DATA_END, CONFIG_POST_IO_PORT); > Instead of modifying the common code, can we modify the simnow_tx_byte method to write the BEGIN byt […] I started with this approach, but soon realized that not only performance affected (in current version of the patch simnow is on par with real HW), but also the logs are much harder to read as postcodes are getting mixed in. If sentinel values added per line and not per byte, then the logs are identical. File src/console/Kconfig: https://review.coreboot.org/c/coreboot/+/61311/comment/9aaeaa81_b1738d89 PS5, Line 489: config CONSOLE_AMD_IO_PORT > Why is that AMD specific? (If so, it needs to be clarified in the commit message. […] The sentinel values are AMD specific, I will correct the commit message. File src/console/printk.c: https://review.coreboot.org/c/coreboot/+/61311/comment/fadb3b33_bbd267c0 PS4, Line 112: outl(AMD_IO_PORT_DATA_BEGIN, CONFIG_POST_IO_PORT); > Hi, Nico and Julius, thank you very much for reviewing. […] Done File src/include/console/io_port.h: PS5: > Can we rename this to simnow. […] The feature is not Simnow specific, it can be used with real HW. The io_port.h is to have one more way to output serial logs, this part is not AMD specific, community may also use this and adjust the code so they use io_port.h too. File src/soc/amd/sabrina/bootblock.c: https://review.coreboot.org/c/coreboot/+/61311/comment/eb90c714_3a5790d9 PS5, Line 39: if (CONFIG(CONSOLE_AMD_IO_PORT)) : outl(AMD_IO_PORT_DATA_BEGIN, CONFIG_POST_IO_PORT); > This should be done as part of the console_init Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87afea28535e03ef39e104e353255a901015973b Gerrit-Change-Number: 61311 Gerrit-PatchSet: 5 Gerrit-Owner: Alexey Buyanov <al3xbuy(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexey Buyanov <alexey.buyanov(a)amd.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Apr 2022 19:41:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexey Buyanov <al3xbuy(a)gmail.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
by Prashant Malani (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63793 ) Change subject: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpigen_usb.c: https://review.coreboot.org/c/coreboot/+/63793/comment/b1d04495_5e9e3785 PS1, Line 109: retimer-switch There is a chance this might get renamed, depending on how things shake out with the kernel driver review upstream. I'm hoping that it's not too inconvenient if we change it in the future, since there is no platform with the EC Mux device in it's devicetree yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/63793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Gerrit-Change-Number: 63793 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 22 Apr 2022 19:01:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn
by Prashant Malani (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Prashant Malani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63793 ) Change subject: ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn ...................................................................... ec/google/chromeec/ec_acpi: Add retimer handle to Type C conn Some platforms have retimers which can be configured via the EC. Add a handle to these retimer devices to the Type C connector device, using devicetree references. BUG=b:208883648 TEST=Verify disassembled SSDT on brya. BRANCH=None Signed-off-by: Prashant Malani <pmalani(a)chromium.org> Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e --- M src/acpi/acpigen_usb.c M src/ec/google/chromeec/chip.h M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_usb.h 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63793/1 diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index e32dfc4..e71e6da 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -106,6 +106,7 @@ add_device_ref(dsd, "orientation-switch", config->orientation_switch); add_device_ref(dsd, "usb-role-switch", config->usb_role_switch); add_device_ref(dsd, "mode-switch", config->mode_switch); + add_device_ref(dsd, "retimer-switch", config->retimer_switch); } void acpigen_write_typec_connector(const struct typec_connector_class_config *config, diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 3915cf9..bb03e57 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -11,6 +11,7 @@ struct ec_google_chromeec_config { /* Pointer to PMC Mux connector for each Type-C port */ DEVTREE_CONST struct device *mux_conn[MAX_TYPEC_PORTS]; + DEVTREE_CONST struct device *retimer_conn[MAX_TYPEC_PORTS]; }; #endif /* EC_GOOGLE_CHROMEEC_CHIP_H */ diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 7f94626..69b1078 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -195,6 +195,7 @@ .orientation_switch = config->mux_conn[i], .usb_role_switch = config->mux_conn[i], .mode_switch = config->mux_conn[i], + .retimer_switch = config->retimer_conn[i], .pld = &pld, }; diff --git a/src/include/acpi/acpigen_usb.h b/src/include/acpi/acpigen_usb.h index 8042874..9a13a7f 100644 --- a/src/include/acpi/acpigen_usb.h +++ b/src/include/acpi/acpigen_usb.h @@ -41,6 +41,9 @@ * host or device, for the USB port * @mode_switch: Reference to the ACPI device that controls routing of data lines to * various endpoints (xHCI, DP, etc.) on the SoC. + * @retimer_switch: Reference to the ACPI device that controls the configuration + * of the retimer in the Type C signal chain. + * various endpoints (xHCI, DP, etc.) on the SoC. * @pld: Reference to PLD information. */ struct typec_connector_class_config { @@ -53,6 +56,7 @@ const struct device *orientation_switch; const struct device *usb_role_switch; const struct device *mode_switch; + const struct device *retimer_switch; const struct acpi_pld *pld; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/63793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e Gerrit-Change-Number: 63793 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Add EC Mux device
by Prashant Malani (Code Review) 22 Apr '22

22 Apr '22

Prashant Malani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63792 ) Change subject: ec/google/chromeec: Add EC Mux device ...................................................................... ec/google/chromeec: Add EC Mux device Introduce an EC Mux ACPI device, which will control retimer and discrete (off-AP) mux configuration. BUG=b:208883648 TEST=None BRANCH=None Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Signed-off-by: Prashant Malani <pmalani(a)chromium.org> --- M src/ec/google/chromeec/Makefile.inc A src/ec/google/chromeec/mux/Kconfig A src/ec/google/chromeec/mux/Makefile.inc A src/ec/google/chromeec/mux/conn/Makefile.inc A src/ec/google/chromeec/mux/conn/conn.c A src/ec/google/chromeec/mux/mux.c 6 files changed, 99 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63792/1 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 23e7b3d..f6c53d3 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -2,6 +2,7 @@ subdirs-y += audio_codec subdirs-y += i2c_tunnel +subdirs-y += mux bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_BOARDID) += ec_boardid.c diff --git a/src/ec/google/chromeec/mux/Kconfig b/src/ec/google/chromeec/mux/Kconfig new file mode 100644 index 0000000..654ff82 --- /dev/null +++ b/src/ec/google/chromeec/mux/Kconfig @@ -0,0 +1,11 @@ +if EC_GOOGLE_CHROMEEC + +config EC_GOOGLE_CHROMEEC_MUX + bool + depends on HAVE_ACPI_TABLES + help + This enables the Cros EC Mux driver that is required to fill the + SSDT nodes for the EC Mux platform device which is used to + configure Type C muxes and retimers. + +endif diff --git a/src/ec/google/chromeec/mux/Makefile.inc b/src/ec/google/chromeec/mux/Makefile.inc new file mode 100644 index 0000000..c4cef75 --- /dev/null +++ b/src/ec/google/chromeec/mux/Makefile.inc @@ -0,0 +1,2 @@ +subdirs-y += conn +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MUX) += mux.c diff --git a/src/ec/google/chromeec/mux/conn/Makefile.inc b/src/ec/google/chromeec/mux/conn/Makefile.inc new file mode 100644 index 0000000..1f837ca --- /dev/null +++ b/src/ec/google/chromeec/mux/conn/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_MUX) += conn.c diff --git a/src/ec/google/chromeec/mux/conn/conn.c b/src/ec/google/chromeec/mux/conn/conn.c new file mode 100644 index 0000000..43f5595 --- /dev/null +++ b/src/ec/google/chromeec/mux/conn/conn.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> + +static const char *conn_acpi_name(const struct device *dev) +{ + static char name[5]; + snprintf(name, sizeof(name), "CON%1X", dev->path.generic.id); + return name; +} + +static void conn_fill_ssdt(const struct device *dev) +{ + const char *name; + name = acpi_device_name(dev); + if (!name) + return; + + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(name); + + acpigen_write_name_integer("_ADR", dev->path.generic.id); + + acpigen_write_device_end(); + acpigen_write_scope_end(); +} + +static struct device_operations conn_dev_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = conn_acpi_name, + .acpi_fill_ssdt = conn_fill_ssdt, +}; + +static void conn_enable(struct device *dev) +{ + dev->ops = &conn_dev_ops; +} + +struct chip_operations ec_google_chromeec_mux_conn_ops = { + CHIP_NAME("CrosEC Type C Mux device") + .enable_dev = conn_enable, +}; diff --git a/src/ec/google/chromeec/mux/mux.c b/src/ec/google/chromeec/mux/mux.c new file mode 100644 index 0000000..9324d2e --- /dev/null +++ b/src/ec/google/chromeec/mux/mux.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> + +#define GOOGLE_CHROMEEC_MUX_DEVICE_HID "GOOG001A" +#define GOOGLE_CHROMEEC_MUX_DEVICE_NAME "ECMX" + +static void mux_fill_ssdt(const struct device *dev) +{ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(GOOGLE_CHROMEEC_MUX_DEVICE_NAME); + acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_MUX_DEVICE_HID); + acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller " + "Mux & Retimer control"); + + acpigen_write_device_end(); + acpigen_write_scope_end(); +} + +static const char *mux_acpi_name(const struct device *dev) +{ + return GOOGLE_CHROMEEC_MUX_DEVICE_NAME; +} + +static struct device_operations mux_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = mux_acpi_name, + .acpi_fill_ssdt = mux_fill_ssdt, + .scan_bus = scan_static_bus, +}; + +static void mux_enable(struct device *dev) +{ + dev->ops = &mux_ops; +} + +struct chip_operations ec_google_chromeec_mux_ops = { + CHIP_NAME("CrosEC Type C Mux device") + .enable_dev = mux_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/63792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2022810292783583ee5f09ce29a63b96686dbb8 Gerrit-Change-Number: 63792 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/device/i2c_simple: add i2c_read_eeprom_bytes function
by Fred Reitberger (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Raul Rangel, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63791 ) Change subject: include/device/i2c_simple: add i2c_read_eeprom_bytes function ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa Gerrit-Change-Number: 63791 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Apr 2022 18:44:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/device/i2c_simple: add i2c_read_eeprom_bytes function
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63791 ) Change subject: include/device/i2c_simple: add i2c_read_eeprom_bytes function ...................................................................... include/device/i2c_simple: add i2c_read_eeprom_bytes function To read data from an I2C EEPROM, first the two offset bytes are sent to the EEPROM and then the data bytes are read from the EEPROM. The main difference to i2c_read_bytes is that that function will only send one offset byte to the I2C device. TEST=Reading the contents of an EEPROM on the AMD Chausie board works Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa --- M src/include/device/i2c_simple.h 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63791/1 diff --git a/src/include/device/i2c_simple.h b/src/include/device/i2c_simple.h index 8f389b3..8d15474 100644 --- a/src/include/device/i2c_simple.h +++ b/src/include/device/i2c_simple.h @@ -142,4 +142,32 @@ return i2c_transfer(bus, &seg, 1); } +/** + * Read multi-bytes from an eeprom with two address bytes with + * two segments in one frame + * + * [start][slave addr][w][register high addr][register low addr] + * [start][slave addr][r][data...][stop] + */ +static inline int i2c_read_eeprom_bytes(unsigned int bus, uint8_t slave, uint16_t offset, + uint8_t *data, int len) +{ + struct i2c_msg seg[2]; + uint8_t eeprom_offset[2]; + + eeprom_offset[0] = offset >> 8; + eeprom_offset[1] = offset & 0xff; + + seg[0].flags = 0; + seg[0].slave = slave; + seg[0].buf = eeprom_offset; + seg[0].len = sizeof(eeprom_offset); + seg[1].flags = I2C_M_RD; + seg[1].slave = slave; + seg[1].buf = data; + seg[1].len = len; + + return i2c_transfer(bus, seg, ARRAY_SIZE(seg)); +} + #endif /* _DEVICE_I2C_SIMPLE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa Gerrit-Change-Number: 63791 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/acpi: Fill PEP S0 mask on failure
by Evan Green (Code Review) 22 Apr '22

22 Apr '22

Evan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63790 ) Change subject: soc/intel/common/block/acpi: Fill PEP S0 mask on failure ...................................................................... soc/intel/common/block/acpi: Fill PEP S0 mask on failure There is a bug floating around where communciation with the PMC fails after transitions through S3/S4/S5. This CL does not address that issue. However in working with error cases presented by a failing PMC, we're forced into an early return in read_pmc_lpm_requirements(), which sets up _DSM buffers in the SSDT for the PEP device. The function itself returns void, so the error is swallowed regardless. However returning early is not the appropriate action because it causes the size of the buffer written into the _DSM method to change. This causes the SSDT to change size and layout across an S3 or S4 transition, which results in mayhem in the kernel, as the kernel is not expecting these tables to change out from under it. Instead of returning early, it's better to simply print the error and keep going, attaching a zeroed out buffer for the substate requirements. This results in an empty requirements mask for all states. From what I can see in the kernel this is no more broken than today's behavior, as this buffer seems to only be used for printing a debugfs file. In fact in this particular case the kernel doesn't even notice, as this buffer is copied out at boot, and not refreshed at resume. BUG=b:230031158 TEST=hibernate and resume on Primus4ES Signed-off-by: Evan Green <evgreen(a)chromium.org> Change-Id: Ibe35d50b350b1b96dea313dfcbd00745970c16ab --- M src/soc/intel/common/block/acpi/pep.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63790/1 diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index c7f1270..b83b714 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -56,8 +56,6 @@ if (result != CB_SUCCESS) { printk(BIOS_ERR, "Failed to retrieve LPM substate registers" "from LPM, substate %zu, reg %zu\n", i, j); - free(reg); - return; } uint32_t *ptr = reg + i * lpm->num_req_regs + j; -- To view, visit https://review.coreboot.org/c/coreboot/+/63790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe35d50b350b1b96dea313dfcbd00745970c16ab Gerrit-Change-Number: 63790 Gerrit-PatchSet: 1 Gerrit-Owner: Evan Green <evgreen(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63737 ) Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Gerrit-Change-Number: 63737 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 17:50:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function
by Tim Wawrzynczak (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63737 ) Change subject: soc/intel/alderlake: Refactor `pmc_lockdown_cfg` function ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36 Gerrit-Change-Number: 63737 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 16:11:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create mithrax variant
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: John Su, Anson Tseng, Nick Vaccaro, Ricky Chang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63776 ) Change subject: mb/google/brya: Create mithrax variant ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb Gerrit-Change-Number: 63776 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Anson Tseng <ansontseng(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Anson Tseng <ansontseng(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 16:11:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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