coreboot-gerrit April 2022

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Change in coreboot[master]: mb/amd/chausie: Auto-detect DDI type
by Fred Reitberger (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63795 ) Change subject: mb/amd/chausie: Auto-detect DDI type ...................................................................... mb/amd/chausie: Auto-detect DDI type Read the EEPROM to detect the DDI type. BUG=225139014 TEST=Boot chausie and correctly detect display card type Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/chausie/port_descriptors.c 2 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/63795/1 diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 4a0c5b0..09b8500 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -24,6 +24,11 @@ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" + register "i2c[0].early_init" = "1" + register "i2c[1].early_init" = "1" + register "i2c[2].early_init" = "1" + register "i2c[3].early_init" = "1" + # I2C Pad Control RX Select Configuration register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V" register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V" diff --git a/src/mainboard/amd/chausie/port_descriptors.c b/src/mainboard/amd/chausie/port_descriptors.c index 4a8a0fd..aacc6e5 100644 --- a/src/mainboard/amd/chausie/port_descriptors.c +++ b/src/mainboard/amd/chausie/port_descriptors.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> +#include <device/i2c_simple.h> #include <soc/gpio.h> #include <soc/platform_descriptors.h> #include <types.h> @@ -47,7 +49,7 @@ }, }; -static const fsp_ddi_descriptor chausie_ddi_descriptors[] = { +static fsp_ddi_descriptor chausie_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, .aux_index = DDI_AUX1, @@ -75,10 +77,47 @@ } }; +static uint8_t get_ddi1_type(void) +{ + const uint8_t eeprom_i2c_bus = 2; + const uint8_t eeprom_i2c_address = 0x55; + const uint16_t eeprom_connector_type_offset = 2; + uint8_t eeprom_connector_type_data[2]; + uint16_t connector_type; + + if (i2c_read_eeprom_bytes(eeprom_i2c_bus, eeprom_i2c_address, eeprom_connector_type_offset, + eeprom_connector_type_data, sizeof(eeprom_connector_type_data))) { + printk(BIOS_NOTICE, "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; + + switch (connector_type) { + case 0xc: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + break; + case 0x13: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + break; + case 0x14: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + break; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", connector_type); + return DDI_UNUSED_TYPE; + } +} + void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { + chausie_ddi_descriptors[1].connector_type = get_ddi1_type(); + *dxio_descs = chausie_dxio_descriptors; *dxio_num = ARRAY_SIZE(chausie_dxio_descriptors); *ddi_descs = chausie_ddi_descriptors; -- To view, visit https://review.coreboot.org/c/coreboot/+/63795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007 Gerrit-Change-Number: 63795 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/chausie/*: Add EC support
by Fred Reitberger (Code Review) 22 Apr '22

22 Apr '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63794 ) Change subject: mb/amd/chausie/*: Add EC support ...................................................................... mb/amd/chausie/*: Add EC support Add support for the chausie EC. Use EC to configure default board GPIO settings. Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/mainboard/amd/chausie/Kconfig M src/mainboard/amd/chausie/Makefile.inc M src/mainboard/amd/chausie/bootblock.c M src/mainboard/amd/chausie/devicetree.cb A src/mainboard/amd/chausie/ec.c A src/mainboard/amd/chausie/ec.h 6 files changed, 89 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63794/1 diff --git a/src/mainboard/amd/chausie/Kconfig b/src/mainboard/amd/chausie/Kconfig index 88c4d0a..b76c87a 100644 --- a/src/mainboard/amd/chausie/Kconfig +++ b/src/mainboard/amd/chausie/Kconfig @@ -6,6 +6,7 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME + select EC_ACPI select SOC_AMD_SABRINA select SOC_AMD_COMMON_BLOCK_USE_ESPI select AMD_SOC_CONSOLE_UART diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index 1e1b6d4..2560886 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -2,6 +2,7 @@ bootblock-y += bootblock.c bootblock-y += early_gpio.c +bootblock-y += ec.c romstage-y += port_descriptors.c diff --git a/src/mainboard/amd/chausie/bootblock.c b/src/mainboard/amd/chausie/bootblock.c index f768f3f..7e66a33 100644 --- a/src/mainboard/amd/chausie/bootblock.c +++ b/src/mainboard/amd/chausie/bootblock.c @@ -1,9 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <soc/espi.h> #include "gpio.h" +#include "ec.h" void bootblock_mainboard_early_init(void) { mainboard_program_early_gpios(); + + espi_switch_to_spi1_pads(); +} + +void bootblock_mainboard_init(void) +{ + chausie_ec_init(); } diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 85e9c08..4a0c5b0 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -2,7 +2,15 @@ chip soc/amd/sabrina register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN, + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x3f8, + .size = 8, + }, + .generic_io_range[1] = { + .base = 0x600, + .size = 256, + }, .io_mode = ESPI_IO_MODE_QUAD, .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, .crc_check_enable = 1, diff --git a/src/mainboard/amd/chausie/ec.c b/src/mainboard/amd/chausie/ec.c new file mode 100644 index 0000000..4d451d0 --- /dev/null +++ b/src/mainboard/amd/chausie/ec.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ec/acpi/ec.h> +#include "ec.h" + +#define CHAUSIE_EC_CMD 0x666 +#define CHAUSIE_EC_DATA 0x662 + +#define EC_GPIO_3_ADDR 0xA3 +#define EC_GPIO_LOM_RESET_AUX (1 << 1) + +#define EC_GPIO_7_ADDR 0xA7 +#define EC_GPIO_DT_PWREN (1 << 2) +#define EC_GPIO_WWAN_MODULE_RST (1 << 5) + +#define EC_GPIO_8_ADDR 0xA8 +#define EC_GPIO_SMBUS0_EN (1 << 0) + +#define EC_GPIO_A_ADDR 0xAA +#define EC_GPIO_WWAN_PWREN (1 << 3) +#define EC_GPIO_M2_SSD0_PWREN (1 << 6) +#define EC_GPIO_LOM_PWREN (1 << 7) + +#define EC_GPIO_C_ADDR 0xAC +#define EC_GPIO_DT_N_WLAN_SW (1 << 1) +#define EC_GPIO_MP2_SEL (1 << 2) +#define EC_GPIO_WWAN_N_LOM_SW (1 << 3) + +static void configure_ec_gpio(void) +{ + uint8_t tmp; + + tmp = ec_read(EC_GPIO_3_ADDR); + tmp |= EC_GPIO_LOM_RESET_AUX; + ec_write(EC_GPIO_3_ADDR, tmp); + + tmp = ec_read(EC_GPIO_7_ADDR); + tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN; + ec_write(EC_GPIO_7_ADDR, tmp); + + tmp = ec_read(EC_GPIO_8_ADDR); + tmp |= EC_GPIO_SMBUS0_EN; + ec_write(EC_GPIO_8_ADDR, tmp); + + tmp = ec_read(EC_GPIO_A_ADDR); + tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; + ec_write(EC_GPIO_A_ADDR, tmp); + + tmp = ec_read(EC_GPIO_C_ADDR); + tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; + ec_write(EC_GPIO_C_ADDR, tmp); +} + +void chausie_ec_init(void) +{ + printk(BIOS_INFO, "chausie_ec_init\n"); + ec_set_ports(CHAUSIE_EC_CMD, CHAUSIE_EC_DATA); + configure_ec_gpio(); +} + diff --git a/src/mainboard/amd/chausie/ec.h b/src/mainboard/amd/chausie/ec.h new file mode 100644 index 0000000..5e78a91 --- /dev/null +++ b/src/mainboard/amd/chausie/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CHAUSIE_EC_H +#define CHAUSIE_EC_H + +void chausie_ec_init(void); + +#endif // CHAUSIE_EC_H -- To view, visit https://review.coreboot.org/c/coreboot/+/63794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb Gerrit-Change-Number: 63794 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd: Remove unused <cbmem.h>
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61055 ) Change subject: soc/amd: Remove unused <cbmem.h> ...................................................................... soc/amd: Remove unused <cbmem.h> Change-Id: Ic8fea24f5f830294ce5b94374ce64d7ca2013c9c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61055 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/stoneyridge/fch.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c index e793e1b..2b2c6de 100644 --- a/src/soc/amd/stoneyridge/fch.c +++ b/src/soc/amd/stoneyridge/fch.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <cbmem.h> #include <acpi/acpi_gnvs.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/aoac.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/61055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8fea24f5f830294ce5b94374ce64d7ca2013c9c Gerrit-Change-Number: 61055 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd: Remove unused <cbmem.h>
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Raul Rangel, Marshall Dawson, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61055 ) Change subject: soc/amd: Remove unused <cbmem.h> ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8fea24f5f830294ce5b94374ce64d7ca2013c9c Gerrit-Change-Number: 61055 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 22 Apr 2022 21:38:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Remove unused <cbmem.h>
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61056 ) Change subject: soc/intel: Remove unused <cbmem.h> ...................................................................... soc/intel: Remove unused <cbmem.h> Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61056 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/crashlog.c M src/soc/intel/apollolake/chip.c M src/soc/intel/broadwell/romstage.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/crashlog_lib.c 6 files changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index ee66730..7bfa70b 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <cbmem.h> #include <intelblocks/crashlog.h> #include <string.h> #include <soc/crashlog.h> diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3ee4920..c98d1c4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -3,7 +3,6 @@ #include <acpi/acpi.h> #include <bootsplash.h> #include <bootstate.h> -#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mp.h> #include <device/mmio.h> diff --git a/src/soc/intel/broadwell/romstage.c b/src/soc/intel/broadwell/romstage.c index 09a7283..65fe7ec 100644 --- a/src/soc/intel/broadwell/romstage.c +++ b/src/soc/intel/broadwell/romstage.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <arch/romstage.h> -#include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1726cd7..7051f51 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootsplash.h> -#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 7c77a89..f59b4c3 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootsplash.h> -#include <cbmem.h> #include <fsp/api.h> #include <acpi/acpi.h> #include <console/console.h> diff --git a/src/soc/intel/tigerlake/crashlog_lib.c b/src/soc/intel/tigerlake/crashlog_lib.c index aec4aef..bde641d 100644 --- a/src/soc/intel/tigerlake/crashlog_lib.c +++ b/src/soc/intel/tigerlake/crashlog_lib.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <cbmem.h> #include <intelblocks/crashlog.h> #include <string.h> #include <soc/crashlog.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/61056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529c822c9e952dae6613d3de64f6709e0fd9b385 Gerrit-Change-Number: 61056 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/purism/librem_mini: Rework front status LED to show all disk activity
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63749 ) Change subject: mb/purism/librem_mini: Rework front status LED to show all disk activity ...................................................................... mb/purism/librem_mini: Rework front status LED to show all disk activity The front status LED on the Librem Mini is driven by the SATALED# GPIO line configured for native function, so only shows disk activity for SATA drives, but not NVMe. To allow it to show disk activity for NVMe drives as well, reconfigure the GPIO as GPIO-OUT (rather than native function), and configure it via ACPI so that the linux gpio-leds driver will attach and use it accordingly. This has the added benefit of allowing the user to reconfigure the LED as they see fit via sysfs. Test: boot Linux (PureOS) on Librem Mini v2 with NVMe drive, observe status LED blinks during periods of disk activity (tested via 'stress'). Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63749 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c M src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl 2 files changed, 53 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 08134e0..24ed2be 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -539,8 +539,8 @@ /* GPP_E7 - NC */ PAD_NC(GPP_E7, NONE), - /* GPP_E8 - SATALED# */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + /* GPP_E8 - STATUSLED# */ + PAD_CFG_GPO(GPP_E8, 1, PLTRST), /* GPP_E9 - USB2_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl index 0c9a76b..727a9d4 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/acpi/variant.asl @@ -14,3 +14,54 @@ } } } + +Scope (\_SB) +{ + Device (LEDS) + { + Name (_HID, "PRP0001") + Name (_DDN, "GPIO LEDs device") + + Name (_CRS, ResourceTemplate () { + GpioIo ( + Exclusive, // Not shared + PullNone, // No need for pulls + 0, // Debounce timeout + 0, // Drive strength + IoRestrictionOutputOnly, // Only used as output + "\\_SB.PCI0.GPIO", // GPIO controller + 0) // Must be 0 + { + 296, // GPP_E8 - STATUSLED# + } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "compatible", Package() { "gpio-leds" } }, + }, + ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"led-0", "LED0"}, + } + }) + + /* + * For more information about these bindings see: + * Documentation/devicetree/bindings/leds/common.yaml, + * Documentation/devicetree/bindings/leds/leds-gpio.yaml and + * Documentation/firmware-guide/acpi/gpio-properties.rst. + */ + Name (LED0, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"label", "blue:status"}, + Package () {"default-state", "keep"}, + Package () {"linux,default-trigger", "disk-activity"}, + Package () {"gpios", Package () {^LEDS, 0, 0, 1}}, + Package () {"retain-state-suspended", 1}, + } + }) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34c2a5f3fd1038266f4514544abfc1020da6f85b Gerrit-Change-Number: 63749 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption ...................................................................... soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption According to Intel TA#724456, work around the higher SoC power consumption in S0iX when CNVI has background activity. BUG=b:201263040 TEST=Turn on this setting and build and verify on Drawcia. The SLP_S0 toggling become slower or gone at the same CNVI background activity. Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63675 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/jasperlake/include/soc/pmc.h 3 files changed, 23 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f3e7240..398fe71 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -421,6 +421,19 @@ CD_CLOCK_652_8_MHZ = 9, } cd_clock; + /* + * This is a workaround to mitigate higher SoC power consumption in S0ix + * when the CNVI has background activity. + * + * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in + * cppmvric1 register to 0) will break CNVI timing. + * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and + * AX201 (HrP2) + * + * true: Enabled (fewer wakes, lower power) + * false: Disabled (more wakes, higher power) + */ + bool cnvi_reduce_s0ix_pwr_usage; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index a3d4328..3b0d497 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -59,6 +59,11 @@ reg32 = read32(pmcbase + CPPMVRIC3); reg32 &= ~USBSUSPGQDIS; write32(pmcbase + CPPMVRIC3, reg32); + + if (config->cnvi_reduce_s0ix_pwr_usage) { + setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS); + setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0)); + } } pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 1df2c63..1922657 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -121,9 +121,14 @@ #define SLP_S0_RES 0x193c +#define CORE_SPARE_GCR_0 0x195C + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC2 0x1B4C +#define CNVIVNNAONREQQDIS (1 << 26) + #define CPPMVRIC3 0x1E4C #define USBSUSPGQDIS (1 << 15) -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 6 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/i945/memmap.c: Fix TOLUD bit field mask
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63752 ) Change subject: nb/intel/i945/memmap.c: Fix TOLUD bit field mask ...................................................................... nb/intel/i945/memmap.c: Fix TOLUD bit field mask Register TOLUD is defined as bit field 7:3 (section 5.1.26, page 103, i945GM datasheet), fix the mask accordingly. Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49 Signed-off-by: Petr Cvek <petrcvekcz(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63752 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1dea21c..58e29c8 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -40,7 +40,7 @@ /* IGD enabled, get top of Memory from BSM register */ tom = pci_read_config32(IGD_DEV, BSM); else - tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24; + tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf8) << 24; /* subtract TSEG size */ tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC)); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49 Gerrit-Change-Number: 63752 Gerrit-PatchSet: 4 Gerrit-Owner: Petr Cvek <petrcvekcz(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: enable warm reset functionality
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63741 ) Change subject: soc/amd/sabrina: enable warm reset functionality ...................................................................... soc/amd/sabrina: enable warm reset functionality Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force resets to be cold) forced all resets on Cezanne to be cold resets to work around a bug. Since the bug is fixed on Sabrina, this workaround copied over from the Cezanne code isn't needed here, so sort-of revert what the patch referenced above changed for Cezanne in the Sabrina code. BUG=b:229105416 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/sabrina/fch.c M src/soc/amd/sabrina/reset.c 2 files changed, 1 insertion(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c index 9be7dd8..a768989 100644 --- a/src/soc/amd/sabrina/fch.c +++ b/src/soc/amd/sabrina/fch.c @@ -127,11 +127,6 @@ PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -198,7 +193,6 @@ void fch_init(void *chip_info) { - fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/sabrina/reset.c b/src/soc/amd/sabrina/reset.c index 90fedda..28e60b6 100644 --- a/src/soc/amd/sabrina/reset.c +++ b/src/soc/amd/sabrina/reset.c @@ -19,9 +19,7 @@ void do_warm_reset(void) { - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); + /* Assert reset signals only. */ outb(RST_CPU | SYS_RST, RST_CNT); } 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Gerrit-Change-Number: 63741 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: enable warm reset functionality
by Felix Held (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63741 ) Change subject: soc/amd/sabrina: enable warm reset functionality ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Reboot works. So does `echo c > /proc/sysrq-trigger`. […] thanks for testing -- To view, visit https://review.coreboot.org/c/coreboot/+/63741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Gerrit-Change-Number: 63741 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 21:11:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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