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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
soc/intel/cmn/lockdown: Perform SA lockdown configuration
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
Additionally, this patch enforces SA lockdown configuration for SKL
and ICL as well.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
---
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/common/pch/lockdown/lockdown.c
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/tigerlake/finalize.c
6 files changed, 13 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63518/12
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 )
Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
> SOC_INTEL_COMMON_PCH_BASE also includes icelake, skylake and xeon_xp, would be good to note that this enforces SA lockdown config for those as well
Sure, it's enforcing ICL and SKL but Xeon_xp doesn't select `SOC_INTEL_COMMON_BLOCK_SA` Kconfig hence, added check to avoid compilation issue https://review.coreboot.org/c/coreboot/+/63518/11/src/soc/intel/common/pch/…
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Change subject: lib/spd: Change log prefix for ddr4 params
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> dont' you really just need https://review.coreboot. […]
As I mentioned in the issue, we still lack of jedec official SPD document for the LPDDR5 and DDR5...so IDK... I left an issue as well https://partnerissuetracker.corp.google.com/issues/223341399. Or we can change the stupid stress test to waive the coreboot log error... haha
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Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
SOC_INTEL_COMMON_PCH_BASE also includes icelake, skylake and xeon_xp, would be good to note that this enforces SA lockdown config for those as well
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Change subject: soc/intel/alderlake/acpi/gpio.asl: Add missing GPIO communities
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I believe it is intentional that community 2 and 3 are left out of the ASL, they are not usually exposed to the OS.
Community 2 is GPD pins, and 3 is vGPIO pins, why would the OS need control over those?
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Change subject: mb/google/skyrim: Configure SD card reader power sequence
......................................................................
Patch Set 5:
(3 comments)
File src/mainboard/google/skyrim/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/63739/comment/e4dd9ffc_75d70427
PS5, Line 189: /* SD_AUX_RESET_L */
: PAD_GPO(GPIO_27, LOW),
I think this pin will always get reset, so no need to add it here.
https://review.coreboot.org/c/coreboot/+/63739/comment/aa841415_843acef1
PS5, Line 201: PAD_GPO
Can you try the following: `PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),` also update it in the ramstage list.
https://review.coreboot.org/c/coreboot/+/63739/comment/b231c1e3_86a72cb7
PS5, Line 201: PAD_GPO(GPIO_27, HIGH),
> Yes,remove set HIGH SD card is not working.
I suspect it's a timing issue. How long does the SD controller need after reset is de-asserted before it can be enumerated?
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Change subject: lib/spd: Change log prefix for ddr4 params
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
dont' you really just need https://review.coreboot.org/c/coreboot/+/58101 ?
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Change subject: soc/intel/cmn/lockdown: Perform SA lockdown configuration
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/systemagent/systemagent.c:
https://review.coreboot.org/c/coreboot/+/63518/comment/e7a11fba_2e786caf
PS7, Line 327: if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE))
: sa_lock_pam();
> > > What about the lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT on line 79? Shouldn't this code ta […]
Ack
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