coreboot-gerrit April 2022

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Change in coreboot[master]: soc/amd/noncar: Move amdfwtool args setting to a common place
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63784 ) Change subject: soc/amd/noncar: Move amdfwtool args setting to a common place ...................................................................... soc/amd/noncar: Move amdfwtool args setting to a common place These files are almost identical. Tested with BUILD_TIMELESS=1: binaries stay the same for google/skyrim, google/guybrush and google/zork. Change-Id: Ic69e6e987d6db76cd782dc6f053a6a480dbb6237 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/common/block/cpu/noncar/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/Makefile.inc 6 files changed, 157 insertions(+), 369 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63784/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 8522d3f..9dee9b9 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -363,6 +363,12 @@ If unsure, answer 'n' +config PSP_LOAD_S0I3_FW + bool + default y + help + Select this item to include the S0i3 file into the PSP build. + config PSP_UNLOCK_SECURE_DEBUG bool "Unlock secure debug" default y diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5e2a8ad..5583ebb 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -67,140 +67,10 @@ FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_INIT_ESPI),y) -PSP_SOFTFUSE_BITS += 15 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) -PSP_SOFTFUSE_BITS += 58 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) - -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Cezanne" \ - --flashsize $(CONFIG_ROM_SIZE) \ - --multilevel +AMDFW_SOC_ARGS= --soc-name "Cezanne" --multilevel endif # ($(CONFIG_SOC_AMD_CEZANNE),y) diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index b521bf6..e0e90c4 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -36,6 +36,147 @@ $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ $(AMD_FW_AB_POSITION)) +ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) +# Enable secure debug unlock +PSP_SOFTFUSE_BITS += 0 +OPT_TOKEN_UNLOCK="--token-unlock" +endif + +ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) +PSP_SOFTFUSE_BITS += 7 +endif + +ifeq ($(CONFIG_PSP_INIT_ESPI),y) +PSP_SOFTFUSE_BITS += 15 +endif + +ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) +OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" +else +# Disable MP2 firmware loading +PSP_SOFTFUSE_BITS += 29 +endif + +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 58 +endif + +# Use additional Soft Fuse bits specified in Kconfig +PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) + +ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) +OPT_PSP_LOAD_S0I3_FW="--load-s0i3" +endif + +# type = 0x3a +ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) +PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) +endif + +# type = 0x55 +ifeq ($(CONFIG_HAVE_SPL_FILE),y) +SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) +endif + +# +# BIOS Directory Table items - proper ordering is managed by amdfwtool +# + +# type = 0x60 +PSP_APCB_FILES=$(APCB_SOURCES) + +# type = 0x61 +PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) + +# type = 0x62 +PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img +PSP_ELF_FILE=$(objcbfs)/bootblock.elf +PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') +PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') +# type = 0x63 - construct APOB NV base/size from flash map +# The flashmap section used for this is expected to be named RW_MRC_CACHE +APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) + +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +# type = 0x6B - PSP Shared memory location +ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) +PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) +PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) +endif + +# type = 0x52 - PSP Bootloader Userspace Application (verstage) +PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) +PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) +endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK + + +# Helper function to return a value with given bit set +# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. +set-bit=$(call int-shift-left, 1 $(call _toint,$1)) +PSP_SOFTFUSE=$(shell A=$(call int-add, \ + $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) + +# +# Build the arguments to amdfwtool (order is unimportant). Missing file names +# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. +# + +add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) + +OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) +OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) + +OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) +OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) +OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) +OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) + +OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) +OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) +OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) +OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) + +OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) + +ifeq ($(CONFIG_VBOOT),) +OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) +OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) +endif + +OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) + +# Add all the files listed in the config file +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) + +AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILES_BK) \ + $(OPT_APOB_ADDR) \ + $(OPT_PSP_BIOSBIN_FILE) \ + $(OPT_PSP_BIOSBIN_DEST) \ + $(OPT_PSP_BIOSBIN_SIZE) \ + $(OPT_PSP_SOFTFUSE) \ + --use-pspsecureos \ + $(OPT_PSP_LOAD_MP2_FW) \ + $(OPT_PSP_LOAD_S0I3_FW) \ + $(OPT_WHITELIST_FILE) \ + $(OPT_SPL_TABLE_FILE) \ + $(OPT_PSP_SHAREDMEM_BASE) \ + $(OPT_PSP_SHAREDMEM_SIZE) \ + --combo-capable \ + $(OPT_TOKEN_UNLOCK) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_MICRON_FLAG) \ + --config $(CONFIG_AMDFW_CONFIG_FILE) \ + $(AMDFW_SOC_ARGS) \ + --flashsize $(CONFIG_ROM_SIZE) + $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ $(PSP_VERSTAGE_SIG_FILE) \ @@ -44,7 +185,7 @@ $(AMDFWTOOL) \ $(obj)/fmap_config.h \ $(objcbfs)/bootblock.elf # this target also creates the .map file - $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) + $(if $(PSP_APCB_FILES), ,$(info APCB_SOURCES is not set)) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b7848f7..10288a8 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -71,79 +71,6 @@ FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -ifeq ($(CONFIG_PSP_LOAD_S0I3_FW),y) -OPT_PSP_LOAD_S0I3_FW="--load-s0i3" -endif - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ --instance $(shell printf "%x" $$(($(i)-1))) --apcb ) ) @@ -151,47 +78,6 @@ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ --instance $(shell printf "1%x" $$(($(i)-1))) --apcb ) ) -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) - -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_PSP_APCB_FILES_BK) \ - $(OPT_APOB_ADDR) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - --use-pspsecureos \ - $(OPT_PSP_LOAD_MP2_FW) \ - $(OPT_PSP_LOAD_S0I3_FW) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Picasso" \ - --flashsize $(CONFIG_ROM_SIZE) +AMDFW_SOC_ARGS= --soc-name "Picasso" endif # ($(CONFIG_SOC_AMD_PICASSO),y) diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index db88fe3..e7646b4 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -366,6 +366,12 @@ If unsure, answer 'n' +config PSP_LOAD_S0I3_FW + bool + default y + help + Select this item to include the S0i3 file into the PSP build. + config PSP_UNLOCK_SECURE_DEBUG bool "Unlock secure debug" default y diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index e604142..880d566 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -66,135 +66,14 @@ FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) -PSP_SOFTFUSE_BITS += 7 -endif - -ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) -# Enable secure debug unlock -PSP_SOFTFUSE_BITS += 0 -OPT_TOKEN_UNLOCK="--token-unlock" -endif - -ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) -OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" -else -# Disable MP2 firmware loading -PSP_SOFTFUSE_BITS += 29 -endif - -# Use additional Soft Fuse bits specified in Kconfig -PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) - -# type = 0x3a -ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) -PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) -endif - -# type = 0x55 -ifeq ($(CONFIG_HAVE_SPL_FILE),y) -SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) -endif - -# -# BIOS Directory Table items - proper ordering is managed by amdfwtool -# - -# type = 0x60 -PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) - -# type = 0x61 -PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) - -# type = 0x62 -PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img -PSP_ELF_FILE=$(objcbfs)/bootblock.elf -PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') -PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') - -# type = 0x63 - construct APOB NV base/size from flash map -# The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) - -ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) -# type = 0x6B - PSP Shared memory location -ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) -PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) -PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) -endif - -# type = 0x52 - PSP Bootloader Userspace Application (verstage) -PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) -PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) -endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK - -# Helper function to return a value with given bit set -# Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. -set-bit=$(call int-shift-left, 1 $(call _toint,$1)) -PSP_SOFTFUSE=$(shell A=$(call int-add, \ - $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A) - -# -# Build the arguments to amdfwtool (order is unimportant). Missing file names -# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. -# - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) -OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) - OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) -OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) -OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) -OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) -OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) - -OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) -OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) -OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) -OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) -OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) -OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) -OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) - -OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) - -OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) -OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) - # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) -# Add all the files listed in the config file -POUND_SIGN=$(call strip_quotes, "\#") -DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) - -AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ - $(OPT_APOB_ADDR) \ - $(OPT_PSP_BIOSBIN_FILE) \ - $(OPT_PSP_BIOSBIN_DEST) \ - $(OPT_PSP_BIOSBIN_SIZE) \ - $(OPT_PSP_SOFTFUSE) \ - $(OPT_PSP_LOAD_MP2_FW) \ - --use-pspsecureos \ - --load-s0i3 \ - --combo-capable \ - $(OPT_TOKEN_UNLOCK) \ - $(OPT_WHITELIST_FILE) \ - $(OPT_SPL_TABLE_FILE) \ - $(OPT_PSP_SHAREDMEM_BASE) \ - $(OPT_PSP_SHAREDMEM_SIZE) \ - $(OPT_EFS_SPI_READ_MODE) \ - $(OPT_EFS_SPI_SPEED) \ - $(OPT_EFS_SPI_MICRON_FLAG) \ - --config $(CONFIG_AMDFW_CONFIG_FILE) \ - --soc-name "Sabrina" \ - --flashsize $(CONFIG_ROM_SIZE) \ +AMDFW_SOC_ARGS= --soc-name "Sabrina" \ $(OPT_RECOVERY_AB_SINGLE_COPY) endif # ($(CONFIG_SOC_AMD_SABRINA),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/63784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic69e6e987d6db76cd782dc6f053a6a480dbb6237 Gerrit-Change-Number: 63784 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/noncar: Move adding CBFS files to a common place
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

1 0

Change in coreboot[master]: soc/amd/picasso: Fix always empty AMDFWTOOL args
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63782 ) Change subject: soc/amd/picasso: Fix always empty AMDFWTOOL args ...................................................................... soc/amd/picasso: Fix always empty AMDFWTOOL args APOB_NV_BASE/SIZE on the default apu/amdfw would always be unset, because the ifeq statement is always 0. Change-Id: I64617fa9cf56d0f7da9f2a384437a28e76cfb4d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63782/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 8eef153..fbf466b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -194,11 +194,6 @@ OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) -ifeq ($(CONFIG_VBOOT),) -OPT_APOB0_NV_SIZE=$(OPT_APOB_NV_SIZE) -OPT_APOB0_NV_BASE=$(OPT_APOB_NV_BASE) -endif - OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) # Add all the files listed in the config file @@ -240,8 +235,8 @@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" $(AMDFWTOOL) \ $(AMDFW_COMMON_ARGS) \ - $(OPT_APOB0_NV_SIZE) \ - $(OPT_APOB0_NV_BASE) \ + $(OPT_APOB_NV_SIZE) \ + $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ --location $(shell printf "%#x" $(PICASSO_FWM_POSITION)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/63782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64617fa9cf56d0f7da9f2a384437a28e76cfb4d7 Gerrit-Change-Number: 63782 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/ehl: Remove PSE init 'magic code'
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Praveen HP, Mario Scheithauer, Lean Sheng Tan, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63775 ) Change subject: soc/intel/ehl: Remove PSE init 'magic code' ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63775/comment/b1d3b663_06a8452e PS1, Line 13: With this being done, hence removing the 'magic code' PSE configs : for FSP to run PSE initialization, as there are no document for : such config requirements. lol, I knew it -- To view, visit https://review.coreboot.org/c/coreboot/+/63775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cfacac62cae0a234e4c4927454311454ab01bdd Gerrit-Change-Number: 63775 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Praveen HP <praveen.hodagatta.pranesh(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 10:36:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/corsola: Add RO_GSCVD area to FMAP
by Yu-Ping Wu (Code Review) 22 Apr '22

22 Apr '22

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63781 ) Change subject: mb/google/corsola: Add RO_GSCVD area to FMAP ...................................................................... mb/google/corsola: Add RO_GSCVD area to FMAP This area is used for storing AP RO verification data. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout BRANCH=none Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/corsola/chromeos.fmd 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/63781/1 diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd index 7194632..a8c4dfe 100644 --- a/src/mainboard/google/corsola/chromeos.fmd +++ b/src/mainboard/google/corsola/chromeos.fmd @@ -19,6 +19,7 @@ GBB 0x2f00 RO_FRID 0x100 } + RO_GSCVD 8K RO_VPD(PRESERVE) 32K # At least 16K. } RW_SECTION_A 1500K { -- To view, visit https://review.coreboot.org/c/coreboot/+/63781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47 Gerrit-Change-Number: 63781 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: Add empty string check for OEM string
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Henry Sun, Kangheui Won, Tim Wawrzynczak, Eric Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63772 ) Change subject: ec/google/chromeec: Add empty string check for OEM string ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82 Gerrit-Change-Number: 63772 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 10:01:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Doc/*/gerrit_guidelines.md: Expand fast-track rule
by Eric Lai (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Nico Huber, Paul Menzel, Angel Pons, Arthur Heymans, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63780 ) Change subject: Doc/*/gerrit_guidelines.md: Expand fast-track rule ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Will take care next time :p -- To view, visit https://review.coreboot.org/c/coreboot/+/63780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161 Gerrit-Change-Number: 63780 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:57:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit: Add a separate Makefile.inc
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63758 ) Change subject: cpu/x86/64bit: Add a separate Makefile.inc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8da6265b4c810e39a67f5ec27e26eeb26e3679a4 Gerrit-Change-Number: 63758 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:49:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/sa: Add `finalize` operation for systemagent
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 ) Change subject: soc/intel/common/sa: Add `finalize` operation for systemagent ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/63518/comment/1ed2f083_32717d5b PS7, Line 327: if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) : sa_lock_pam(); > > What about the lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT on line 79? Shouldn't this code take that into account as well? > > There potentially could be three cases as below: > > 1. SoC user decides to call FSP Notify Phase API but like to keep `common_config->chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT` > > 2. The SoC user decides to call FSP Notify Phase API and to keep `common_config->chipset_lockdown = CHIPSET_LOCKDOWN_FSP` > > 3. SoC user decides to skip FSP Notify Phase API > > For #1:soc/intel/alderlake/finalize.c function sa_finalize will perform the PAM register lock. > > For #2:FSP takes care of locking using FSP notify phase 2 API > > For #3:This code change src/soc/intel/common/block/systemagent/systemagent.c#325 ensures to lockdown PAM registers using common code, so, we don't need to implement the SoC specific implementation going forward for MTL for example. > > Also, PAM register attribute is RW/L, once programmed by IA common code as part of `.final` callback, SoC specific implementation doesn't have any significance. I have removed the SoC references now. Please take a look. -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:45:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/sa: Add `finalize` operation for systemagent
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63518 to look at the new patch set (#9). Change subject: soc/intel/common/sa: Add `finalize` operation for systemagent ...................................................................... soc/intel/common/sa: Add `finalize` operation for systemagent The system agent `.final` operation ensures locking the PAM register hence, skip dedicated calling into `sa_lock_pam()` from the SoC `finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL and TGL. Also, convert `sa_lock_pam` function into a static function. BUG=b:211954778 TEST=Able to build google/brya with these changes and coreboot log with this code change as below: [INFO ] Finalize devices... [DEBUG] PCI: 00:00.0 final > localhost ~ # lspci -xxx | less 00:00.0 Host bridge: Device 8086:4601 (rev 04) Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/finalize.c 7 files changed, 17 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63518/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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