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Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/63777/comment/4d30b7e9_efe224a1
PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff)
> > BTW: 0x1ff would be valid here, too. This would follow the previous style better. […]
I mean since the lower byte was alredy 'hard' coded in this define you could proceed the style with bit 8 as well:
#define SPIBAR_HSFSTS_W1C_BITS 0x1ff
Just a nit, up to you
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Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/63777/comment/5bc17dcf_dd4d22b1
PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff)
> BTW: 0x1ff would be valid here, too. This would follow the previous style better.
Sorry Werner, I didn't get this part.
Are you suggesting like this?
#define SPIBAR_HSFSTS_W1C_BITS (0xff | SPIBAR_HSFSTS_SAF_CE)
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Change subject: mb/google/skyrim/var/skyrim: Add audio codec and amp support
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Patch Set 1:
This change is ready for review.
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Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/63777/comment/9a92c733_5ed56f0a
PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff)
BTW: 0x1ff would be valid here, too. This would follow the previous style better.
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Change subject: soc/intel/elkhartlake: Skip FSP Notify APIs
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63762/comment/67bb021e_588922a8
PS4, Line 22: https://review.coreboot.org/c/coreboot/+/60405
Here you could use CB:60405 instead.
Patchset:
PS1:
> > Tested on EHL platform by Werner and it is working fine :) […]
Yes, I do. Thanks for driving this effort Subrata!
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Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/63777/comment/e983ad46_c72e45df
PS1, Line 78: #define SPIBAR_HSFSTS_W1C_BITS (0xff | SPIBAR_HSFSTS_SAF_CE)
> Maybe better […]
Ack
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Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/63777/comment/95f55c2d_93ee0e1d
PS1, Line 78: #define SPIBAR_HSFSTS_W1C_BITS (0xff | SPIBAR_HSFSTS_SAF_CE)
Maybe better
#define SPIBAR_HSFSTS_W1C_BITS (SPIBAR_HSFSTS_SAF_CE | 0xff)
To honor the bit location in the register?
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Change subject: soc/intel/elkhartlake: Skip FSP Notify APIs
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Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63762/comment/99ae4518_9fc8b9a5
PS4, Line 9: CL(60406)
you can use commit (sha) and title of the ADL CL here
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