coreboot-gerrit April 2022

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Change in coreboot[master]: Doc/*/gerrit_guidelines.md: Expand fast-track rule
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63780 ) Change subject: Doc/*/gerrit_guidelines.md: Expand fast-track rule ...................................................................... Doc/*/gerrit_guidelines.md: Expand fast-track rule Commits that fix a recently-introduced regression can be submitted early to minimise the impact of said regression. However, it is important that the commit message properly reflects what is being fixed and what commit introduced the issue. Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/contributing/gerrit_guidelines.md 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63780/1 diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md index 68b5cc4..74f79c0 100644 --- a/Documentation/contributing/gerrit_guidelines.md +++ b/Documentation/contributing/gerrit_guidelines.md @@ -53,7 +53,10 @@ a recently-introduced issue (build, boot or OS-level compatibility, not necessarily identified by coreboot.org facilities). Its commit message has to explain what change introduced the problem and the nature of -the problem so that the emergency need becomes apparent. The change +the problem so that the emergency need becomes apparent. Avoid stating +something like "fix build error" in the commit summary, describe what +the commit does instead, just like any other commit. In addition, it is +recommended to reference the commit that introduced the issue. The change itself should be as limited in scope and impact as possible to make it simple to assess the impact. Such a change can be merged early with 3 Code-Review+2. For emergency fixes that affect a single project (SoC, -- To view, visit https://review.coreboot.org/c/coreboot/+/63780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161 Gerrit-Change-Number: 63780 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Skip FSP Notify APIs
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Mario Scheithauer, Angel Pons, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63762 ) Change subject: soc/intel/elkhartlake: Skip FSP Notify APIs ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63762/comment/78af4183_700c6a07 PS4, Line 9: CL(60406) > you can use commit (sha) and title of the ADL CL here Done https://review.coreboot.org/c/coreboot/+/63762/comment/38f9eaa5_ad19b7f5 PS4, Line 22: https://review.coreboot.org/c/coreboot/+/60405 > Here you could use CB:60405 instead. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 Gerrit-Change-Number: 63762 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:41:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Skip FSP Notify APIs
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Mario Scheithauer, Angel Pons, Lean Sheng Tan. Hello build bot (Jenkins), Subrata Banik, Mario Scheithauer, Angel Pons, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63762 to look at the new patch set (#5). Change subject: soc/intel/elkhartlake: Skip FSP Notify APIs ...................................................................... soc/intel/elkhartlake: Skip FSP Notify APIs Follow this commit CB:60406 of ADL to skip FSP Notify APIs. Elkhart Lake SoC deselects Kconfigs as below: - USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. When deselecting these Kconfigs, cse_final_ready_to_boot() and cse_final_end_of_firmware() in the common cse driver will be used instead as required operations to perform prior to booting to OS. Check out this CL for further info: CB:60405 Additionally, created a helper function `heci_finalize()` to keep HECI related operations separated for easy guarding again config. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 --- M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/63762/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I477c204233f83bc96fd5cd39346bff15ed942dc6 Gerrit-Change-Number: 63762 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/atlas: Fix build error
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Eric Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63773 ) Change subject: mb/prodrive/atlas: Fix build error ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63773/comment/456fe863_83909879 PS3, Line 9: commit c6b041a12e > Commit c6b041a12e (tpm: Refactor TPM Kconfig dimensions) … Maybe we should have something in our guidelines regarding referencing other commits. -- To view, visit https://review.coreboot.org/c/coreboot/+/63773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Gerrit-Change-Number: 63773 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 ) Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:31:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/atlas: Fix build error
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Eric Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63773 ) Change subject: mb/prodrive/atlas: Fix build error ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63773/comment/103700ce_1b7219d9 PS3, Line 7: mb/prodrive/atlas: Fix build error Yes, that's as per our guidelines. https://doc.coreboot.org/contributing/gerrit_guidelines.html > A change can go in without the wait period if its purpose is to fix a recently-introduced issue (build, boot or OS-level compatibility, not necessarily identified by coreboot.org facilities). Its commit message has to explain what change introduced the problem and the nature of the problem so that the emergency need becomes apparent. The change itself should be as limited in scope and impact as possible to make it simple to assess the impact. Such a change can be merged early with 3 Code-Review+2. For emergency fixes that affect a single project (SoC, mainboard, …) it’s strongly recommended to get a review by somebody not involved with that project to ensure that the documentation of the issue is clear enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/63773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff7e20ac271eb5b2afc9061819e2cc0cf2264cbf Gerrit-Change-Number: 63773 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:25:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 ) Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:16:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Angel Pons (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 ) Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:16:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63777 ) Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi_def.h: https://review.coreboot.org/c/coreboot/+/63777/comment/087403fc_43e1ba4b PS2, Line 78: (SPIBAR_HSFSTS_SAF_CE | 0xff) > I mean since the lower byte was alredy 'hard' coded in this define you could proceed the style with bit 8 as well: > > #define SPIBAR_HSFSTS_W1C_BITS 0x1ff > > Just a nit, up to you sure -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 09:01:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63777 to look at the new patch set (#4). Change subject: soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg ...................................................................... soc/intel/cmn/fast_spi: Include SAF_CE (bit 8) bit to clear HSFSTS reg Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS register bit-fields with the W1C attribute. So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear SAF_CE (bit 8). This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include SAF_CE (bit 8). BUG=b:211954778 TEST=Able to build google/brya with this patch and clear SPI controller HSFSTS_CTL register Bits 0 to 4 and 8. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/63777/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8 Gerrit-Change-Number: 63777 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022