coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/apl: Drop cbfs bootblock
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Andrey Petrov. Hello build bot (Jenkins), Sean Rhodes, Angel Pons, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63225 to look at the new patch set (#13). Change subject: soc/intel/apl: Drop cbfs bootblock ...................................................................... soc/intel/apl: Drop cbfs bootblock The bootblock is loaded from IFWI so there is no need to have it in cbfs. Also remove the FIT handling as that is also handled by the IFWI. TESTED: up/squared still boots Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63225/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/63225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e70e080765dd7306074a8cf71c8795b8fbbb8a2 Gerrit-Change-Number: 63225 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apl: Write to cbfs regions using intermediate targets
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Angel Pons, Andrey Petrov. Hello build bot (Jenkins), Sean Rhodes, Angel Pons, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63224 to look at the new patch set (#12). Change subject: soc/intel/apl: Write to cbfs regions using intermediate targets ...................................................................... soc/intel/apl: Write to cbfs regions using intermediate targets This also adds messages when adding the files. Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/Makefile.inc 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63224/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/63224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie812084cc243a18cbc2913804ef2190dd9d6ed9b Gerrit-Change-Number: 63224 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Improve build flow
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Arthur Heymans, Paul Menzel, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56119 ) Change subject: security/intel/cbnt/Makefile.inc: Improve build flow ...................................................................... Patch Set 18: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56119/comment/5020dbfd_f64a7e02 PS11, Line 9: is not needed any longer > It’s not done in patch set 18, I think. > > (Should you repush, please reflow for 72 characters per line.) Sorry. Done now. -- To view, visit https://review.coreboot.org/c/coreboot/+/56119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Gerrit-Change-Number: 56119 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 07:24:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/cbnt/Makefile.inc: Improve build flow
by Arthur Heymans (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Arthur Heymans, Angel Pons. Hello build bot (Jenkins), Sean Rhodes, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56119 to look at the new patch set (#19). Change subject: security/intel/cbnt/Makefile.inc: Improve build flow ...................................................................... security/intel/cbnt/Makefile.inc: Improve build flow Using 'files_added::' is no longer needed as all files have already been added to the build. This has the advantage of showing all final entries in the FIT table and CBFS during the build process as adding the bpm to cbfs and fit is moved earlier. Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/cbnt/Makefile.inc 1 file changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/56119/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/56119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22aa140202f0665b7095a01cb138af4986aa9ac3 Gerrit-Change-Number: 56119 Gerrit-PatchSet: 19 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/ehl: Remove PSE init 'magic code'
by Lean Sheng Tan (Code Review) 22 Apr '22

22 Apr '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63775 ) Change subject: soc/intel/ehl: Remove PSE init 'magic code' ...................................................................... soc/intel/ehl: Remove PSE init 'magic code' Thanks to Werner's and the community presistancy & effort, Intel has finally open sourced PSE FW! https://github.com/intel/pse-fw With this being done, hence removing the 'magic code' PSE configs for FSP to run PSE initialization, as there are no document for such config requirements. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I5cfacac62cae0a234e4c4927454311454ab01bdd --- M src/soc/intel/elkhartlake/fsp_params.c 1 file changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63775/1 diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 2100cc4..9d44bf5 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -181,27 +181,6 @@ params->PchPseAdcSbInterruptEnable = config->PseAdcSbIntEn; params->PchPseLh2PseSbInterruptEnable = config->PseLh2PseSbIntEn; params->PchPseShellEnabled = config->PseShellEn; - - /* - * As a minimum requirement for PSE initialization, the configuration - * of devices below are required as shown. - * TODO: Help needed to find a better way to handle this part of code - * as the settings from devicetree are overwritten here. - * - * Set the ownership of these devices to PSE. These are hardcoded for now, - * if the PSE should be opened one day (hopefully), this can be handled - * much better. - */ - params->PchPseDmaEnable[0] = PSE_Owned; - params->PchPseUartEnable[2] = PSE_Owned; - params->PchPseHsuartEnable[2] = PSE_Owned; - params->PchPseI2cEnable[2] = PSE_Owned; - params->PchPseTimedGpioEnable[0] = PSE_Owned; - params->PchPseTimedGpioEnable[1] = PSE_Owned; - /* Disable PSE DMA Sideband Interrupt for DMA 0 */ - params->PchPseDmaSbInterruptEnable[0] = 0; - /* Set the log output to PSE UART 2 */ - params->PchPseLogOutputChannel = 3; } else { die("PSE enabled but PSE FW not available!\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cfacac62cae0a234e4c4927454311454ab01bdd Gerrit-Change-Number: 63775 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Add Raptor Lake device IDs
by Subrata Banik (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Tim Wawrzynczak, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 ) Change subject: soc/intel: Add Raptor Lake device IDs ...................................................................... Patch Set 3: (7 comments) File src/include/cpu/intel/cpu_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/230c4d04_c52380d3 PS3, Line 62: 0xb06a2 0xB06A0 is this still a valid `A0` CPUID for RPL ? File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/63750/comment/ab94671d_2890e540 PS3, Line 3078: #define PCI_DID_INTEL_RPL_P_ESPI_0 0x519c : #define PCI_DID_INTEL_RPL_P_ESPI_1 0x519d I could see 0x5180-0x519F are full list of supported eSPI Ids for RPL. https://review.coreboot.org/c/coreboot/+/63750/comment/d4809bbb_73cb5ac9 PS3, Line 3439: #define PCI_DID_INTEL_RPL_P_PCIE_RP1 0xa74d : #define PCI_DID_INTEL_RPL_P_PCIE_RP2 0xa70d : #define PCI_DID_INTEL_RPL_P_PCIE_RP3 0xa72d I could see different IDs for CPU RPs? PCIe* RC 060 (x4) G4 S, P, M 0 / 6 / 0 464Dh PCIe* RC 062 (x4) G4 P 0 / 6 / 2 463Dh PCIe* RC 010 G5 S, P 0 / 1 / 0 460Dh https://review.coreboot.org/c/coreboot/+/63750/comment/420710cb_795bdbd0 PS3, Line 3442: I don't see RPL PCH RPs DIDs here ? https://review.coreboot.org/c/coreboot/+/63750/comment/92db0e5e_992055e6 PS3, Line 3515: what about SATA DID? https://review.coreboot.org/c/coreboot/+/63750/comment/042e50bc_37c92fef PS3, Line 3539: PMC as well ? https://review.coreboot.org/c/coreboot/+/63750/comment/15a5032b_f45afbff PS3, Line 4149: RPL can u use `PCH` name like it's being done for `ADP` line#4143 -- To view, visit https://review.coreboot.org/c/coreboot/+/63750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39e655dec2314a672ea63ba90d8bb3fc53bf77ba Gerrit-Change-Number: 63750 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 07:01:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status
by Werner Zeh (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63625 ) Change subject: soc/intel/cmn/fast_spi: Add API to clear outstanding SPI status ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi.c: https://review.coreboot.org/c/coreboot/+/63625/comment/fe9e8e77_4a02bde0 PS6, Line 437: SPIBAR_HSFSTS_W1C_BITS > > Hmmm, just noticed that this macro is defined as 0xff, so bit 8 isn't cleared by this write. […] I must admitt that Elkhart Lake does define bit 8 as well. Sorry for overseeing it. -- To view, visit https://review.coreboot.org/c/coreboot/+/63625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62adba0d0cef1d4c53b24800f90b4fe76a9d78b7 Gerrit-Change-Number: 63625 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 06:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration
by Werner Zeh (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63692 ) Change subject: soc/intel/alderlake: Implement PCH lock down configuration ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/alderlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/63692/comment/a1735ce0_a2d34d58 PS4, Line 41: if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) : return; : : /* Enable IOSF Primary Trunk Clock Gating */ : pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); In CB:63640 the logic is inverted.To stay consistent it would look like: if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); But up to you. -- To view, visit https://review.coreboot.org/c/coreboot/+/63692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Gerrit-Change-Number: 63692 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 06:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*/*/*.fmd: Start flash at 0
by Erik van den Bogaert (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Stefan Ott, Raul Rangel, Patrick Rudolph, Julius Werner, Arthur Heymans, Jason Glenesk, Sean Rhodes, Marshall Dawson, Christian Walter, Tim Wawrzynczak, Alexander Couzens, Fred Reitberger, Felix Held. Erik van den Bogaert has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63771 ) Change subject: mb/*/*/*.fmd: Start flash at 0 ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac86ef9be6b14817a65bf3a7ccb624d205ca3f99 Gerrit-Change-Number: 63771 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 22 Apr 2022 06:34:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock
by Werner Zeh (Code Review) 22 Apr '22

22 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 ) Change subject: soc/intel/alderlake: Implement PMC feature lock ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/intel/alderlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/63691/comment/bc4958be_fc7797c8 PS4, Line 28: setbits32(pmc_mmio_regs() + PM_CFG, PM_CFG_DBG_MODE_LOCK | > For #22, you can put in the array first or last and do compare the statement once. […] I am not sure that all this tweaks are worth it and will improve code readability. If we are not plan to add several dozens of these I would keep it as it is. -- To view, visit https://review.coreboot.org/c/coreboot/+/63691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Gerrit-Change-Number: 63691 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 22 Apr 2022 06:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022