Attention is currently required from: Rehan Ghori.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62591 )
Change subject: scout: i2c HID driver for Ilitek touchscreen
......................................................................
Patch Set 1:
(3 comments)
File src/mainboard/google/hatch/variants/scout/gpio.c:
https://review.coreboot.org/c/coreboot/+/62591/comment/d302e16d_2297719f
PS1, Line 3: #include <gpio.h>
: #include <baseboard/gpio.h>
: #include <baseboard/variants.h>
: #include <commonlib/helpers.h>
: #include <types.h>
: #include <soc/gpio.h>
: #include <vendorcode/google/chromeos/chromeos.h>
nit: please keep alphabetical, i.e.
```
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
```
File src/mainboard/google/hatch/variants/scout/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62591/comment/2b15b85b_cd897e1d
PS1, Line 389: register "generic.probed" = "1"
Are you running with a ChromeOS kernel? If not, then you will not need this, this is for a patch we keep in our local trees (nacked upstream)
https://review.coreboot.org/c/coreboot/+/62591/comment/808c5b75_44fac343
PS1, Line 392: "GPE0_DW0_16
Shouldn't this be
`DPE0_DW2_16`
?
IIUC, you are trying to refer to GPP_D16 as the wake pin?
DW0 is mapped to A group, DW1 is mapped to C group, DW2 is mapped to the D group, see https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62593 )
Change subject: mb/google/hatch/var/jinlon: Fix disabling iGPU when EPS not present
......................................................................
mb/google/hatch/var/jinlon: Fix disabling iGPU when EPS not present
Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
inadvertently broke jinlon boards without an electronic privacy screen
(EPS) by disabling the parent device (iGPU) instead of the EPS when
determined to be not present via SKU ID.
Fix this by assigning the device alias to the EPS child device, not the
parent (iGPU). Rename the alias for clarity, and clean up the
duplicate device definition for the iGPU by combining them.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/hatch/variants/jinlon/mainboard.c
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 5 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62593/1
diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
index d2e5b43..51ef346 100644
--- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c
+++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
@@ -20,20 +20,20 @@
static void check_for_eps(uint32_t sku_id)
{
- struct device *gfx_dev = DEV_PTR(igpu);
+ struct device *eps_dev = DEV_PTR(eps);
if (eps_sku(sku_id)) {
printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id);
return;
}
- if (!gfx_dev) {
+ if (!eps_dev) {
printk(BIOS_ERR, "Error! No EPS dev, view-angle-management won't work\n");
return;
}
printk(BIOS_INFO, "SKU ID %u doesn't have EPS, disabling...\n", sku_id);
- gfx_dev->enabled = 0;
+ eps_dev->enabled = 0;
}
void variant_devtree_update(void)
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index b3887d4..88c9a54 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -69,10 +69,8 @@
register "ScsEmmcHs400Enabled" = "1"
device domain 0 on
- device pci 02.0 alias igpu on # Integrated Graphics Device
- register "gfx" = "GMA_DEFAULT_PANEL(0)"
- end
device pci 02.0 on
+ register "gfx" = "GMA_DEFAULT_PANEL(0)"
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
@@ -80,7 +78,7 @@
register "device[0].addr" = "0x80010400"
register "device[0].privacy.enabled" = "1"
register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)"
- device generic 0 on end
+ device generic 0 alias eps on end
end
end # Integrated Graphics Device
device pci 14.0 on
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Hello Matt DeVillier,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62592
to review the following change.
Change subject: mb/google/hatch/var/jinlon: Fix EPS disabling procedure
......................................................................
mb/google/hatch/var/jinlon: Fix EPS disabling procedure
It looks like commit ebf1482627 (mb/google/hatch/var/jinlon: Switch to
using device pointers) accidentally switched off the iGPU instead of
the generic device representing the Electronic Privacy Screen (EPS)
below it.
The find_gfx_dev() function used prior to ebf1482627 should have
returned the generic device, too.
Change-Id: Iaf5dcb85fbee4386851f822e0087a92cf3434e47
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Fixes: commit ebf1482627 (mb/google/hatch/var/jinlon: Switch to using device pointers)
---
M src/mainboard/google/hatch/variants/jinlon/mainboard.c
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/62592/1
diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
index d2e5b43..51ef346 100644
--- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c
+++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
@@ -20,20 +20,20 @@
static void check_for_eps(uint32_t sku_id)
{
- struct device *gfx_dev = DEV_PTR(igpu);
+ struct device *eps_dev = DEV_PTR(eps);
if (eps_sku(sku_id)) {
printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id);
return;
}
- if (!gfx_dev) {
+ if (!eps_dev) {
printk(BIOS_ERR, "Error! No EPS dev, view-angle-management won't work\n");
return;
}
printk(BIOS_INFO, "SKU ID %u doesn't have EPS, disabling...\n", sku_id);
- gfx_dev->enabled = 0;
+ eps_dev->enabled = 0;
}
void variant_devtree_update(void)
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index b3887d4..a51f892 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -69,7 +69,7 @@
register "ScsEmmcHs400Enabled" = "1"
device domain 0 on
- device pci 02.0 alias igpu on # Integrated Graphics Device
+ device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"
end
device pci 02.0 on
@@ -80,7 +80,7 @@
register "device[0].addr" = "0x80010400"
register "device[0].privacy.enabled" = "1"
register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)"
- device generic 0 on end
+ device generic 0 alias eps on end
end
end # Integrated Graphics Device
device pci 14.0 on
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62424 )
Change subject: Documentation: Move firmware flashing tutorial to tutorial section
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62424/comment/d529665f_9ba6840d
PS2, Line 8:
> Blocking. I will push another patch fixing some links first and this will one will be rebased.
Done
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62474 )
Change subject: util/cbmem: Add FlameGraph-compatible timestamps output
......................................................................
Patch Set 4:
(1 comment)
File src/commonlib/include/commonlib/timestamp_serialized.h:
PS4:
nit: I think this change could be split out by itself, also, if we're going to go with this mechanism in the future, does it make sense to automate creating the strings to represent the timestamp names, e.g. with X-macros or similar?
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Change subject: mb/google/brya/var/kinox: update overridetree
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62553/comment/ff1ac662_afe0dd61
PS6, Line 8:
: 1. Update override devicetree based on schematics.
: 2. ALC5682I-VS is for audio codec.
: 3. Update 15W SOC default PL2/PL4(39W/100W).
: 4. Update DPTF table.
: 5. Enable Bayhub LV2 driver
:
Could you please split these up into their own commits? This is quite a big patch
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Change subject: soc/intel/denverton_ns: enable Denverton to use common SoC XHCI code
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
well, i see that i suffered a bad rebase yesterday from the wrong branch or something, so all the patches that cause an unstable build are bogus and i'll have to be rebasing again using previous versions of the patches.
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Change subject: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix
......................................................................
Patch Set 14: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/brya4es/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/61887/comment/3567b67a_29b2bf42
PS14, Line 142:
nit: no need for a tab here
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