coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Tim Wawrzynczak (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Anil Kumar K, Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62192/comment/02667a67_ff741d7b PS9, Line 142: cse_send_end_of_post_message suggestion: what about `cse_send_eop_with_retries` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 9 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Mar 2022 20:55:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Use heci_reset() in the CSE TX and RX flows
by Tim Wawrzynczak (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Sridhar Siricilla, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62587 ) Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62587/comment/7986733c_a48524d7 PS2, Line 12: cse nit: `CSE`, like you wrote above -- To view, visit https://review.coreboot.org/c/coreboot/+/62587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Gerrit-Change-Number: 62587 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Mar 2022 20:52:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Implement error codes for for heci_send_receive()
by Tim Wawrzynczak (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Subrata Banik, Kane Chen, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62299 ) Change subject: soc/intel/common: Implement error codes for for heci_send_receive() ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62299/comment/50973107_33db41d8 PS4, Line 27: TEST=Build and boot Brya board > Yes, it was done as part of unit testing. Can you add that to the commit msg? -- To view, visit https://review.coreboot.org/c/coreboot/+/62299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Gerrit-Change-Number: 62299 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Mar 2022 20:51:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/driver/wifi: Add _DSM method for DDRRFIM
by Tim Wawrzynczak (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Tim Wawrzynczak. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61020 ) Change subject: src/driver/wifi: Add _DSM method for DDRRFIM ...................................................................... Patch Set 19: (2 comments) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/61020/comment/e29a6347_b6649768 PS19, Line 515: memcpy(dsm, &sar_limits.dsm, sizeof(struct dsm_profile)); one more nit: instead of using memcpy, when the dest and src are the same type, you can have C help you out a little and just do: `*dsm = sar_limits.dsm` https://review.coreboot.org/c/coreboot/+/61020/comment/d6868616_37dac119 PS19, Line 537: dev = dev->link_list->children; : const struct drivers_wifi_generic_config *config = dev->chip_info; : bool is_cnvi_ddr_rfim_enabled; : : is_cnvi_ddr_rfim_enabled = config->enable_cnvi_ddr_rfim; one more thing, you can reuse the function from the previous patch, e.g.. ``` const struct device *generic = dev->link_list->children; if (generic && generic->path.type == DEVICE_PATH_GENERIC) is_cnvi_ddr_rfim_enabled = wifi_generic_cnvi_ddr_rfim_enabled(generic); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 19 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 20:51:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: scout: i2c HID driver for Ilitek touchscreen
by Rehan Ghori (Code Review) 04 Mar '22

04 Mar '22

Rehan Ghori has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62591 ) Change subject: scout: i2c HID driver for Ilitek touchscreen ...................................................................... scout: i2c HID driver for Ilitek touchscreen Add HID driver for i2c-1 for Ilitek touchscreen. BRANCH=None BUG=b:187289163 TEST=Build and flash coreboot; confirm an entry for hidraw for I2C-1 for Ilitek touchscreen. Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd Signed-off-by: Rehan Ghori <rehang(a)google.com> --- M src/mainboard/google/hatch/variants/scout/gpio.c M src/mainboard/google/hatch/variants/scout/overridetree.cb 2 files changed, 21 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62591/1 diff --git a/src/mainboard/google/hatch/variants/scout/gpio.c b/src/mainboard/google/hatch/variants/scout/gpio.c index 218d3db..260acc8 100644 --- a/src/mainboard/google/hatch/variants/scout/gpio.c +++ b/src/mainboard/google/hatch/variants/scout/gpio.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <commonlib/helpers.h> +#include <types.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> static const struct pad_config gpio_table[] = { /* A16 : SD_OC_ODL */ @@ -66,6 +70,8 @@ PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), /* D15 : USI_RST_L */ PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D16 TOUCH_INT */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D16, NONE, PLTRST, LEVEL, INVERT), /* E2 : Not connected */ PAD_NC(GPP_E2, NONE), diff --git a/src/mainboard/google/hatch/variants/scout/overridetree.cb b/src/mainboard/google/hatch/variants/scout/overridetree.cb index 1312966..cc07e2f 100644 --- a/src/mainboard/google/hatch/variants/scout/overridetree.cb +++ b/src/mainboard/google/hatch/variants/scout/overridetree.cb @@ -381,7 +381,21 @@ device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 - device pci 15.1 on end # I2C #1, USI (Touch screen) + device pci 15.1 on # I2C #1, USI (Touch screen) + chip drivers/i2c/hid + register "generic.hid" = ""ILTK0001"" + register "generic.desc" = ""ILITEK Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "600" + register "generic.wake" = "GPE0_DW0_16" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on end + end + end device pci 15.2 on end # I2C #2, SCALER device pci 15.3 on end # I2C #3, TPU device pci 16.0 on end # Management Engine Interface 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd Gerrit-Change-Number: 62591 Gerrit-PatchSet: 1 Gerrit-Owner: Rehan Ghori <rehang(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Sridhar Siricilla (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Nico Huber, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 10: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61380/comment/64328438_5ebc080f PS10, Line 13: rebuilding the coreboot. > `rebuilding coreboot. […] Ack https://review.coreboot.org/c/coreboot/+/61380/comment/1e794313_1141667f PS10, Line 17: The OEM section starts from offset:0xf00 till end of the Descriptor : Region(0xfff). > Either bring up to the previous line or add a blank line between paragraphs Ack File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/61380/comment/9bf76d6e_3b4883a8 PS10, Line 668: if (CONFIG(SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE) && CONFIG(SOC_INTEL_CSE_RW_UPDATE)) : return !is_debug_cse_fw_update_disable(); : : return CONFIG(SOC_INTEL_CSE_RW_UPDATE); > suggestion, does this make the logic a little more clear? […] Ack File src/soc/intel/common/block/debug/debug_feature.c: https://review.coreboot.org/c/coreboot/+/61380/comment/7afcbacf_b339a85d PS10, Line 14: /* Byte location: 0xF00 */ > nit: this comment seems redundant, you have a well-named #define for this If pre_mem_ft member list grows up, then it might be helpful! https://review.coreboot.org/c/coreboot/+/61380/comment/c477f0ed_ecf71e7e PS10, Line 28: pre_mem_debug.cse_fw_update_disable == 1; > It seems the default value for the OEM section is 0xFFFF_FFFF, so if I am thinking correctly, on a n […] When DEBUG_FEATURE Kconfig is enabled, pre_mem_debug.cse_fw_update_disable becomes 0xFF, but expectation is 1 in order to disable the cse fw update. Please note each feature occupies 1 byte, not 1 bit. >As in there is extra work required (go and set that bit in the descriptor) to enable CSE RW update once you enable the Kconfig? This is not intended, please see my above comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Mar 2022 20:08:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add support for PCI MMIO CONFIG access.
by build bot (Jenkins) (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Ravi kumar, Furquan Shaikh, Arthur Heymans, Prasad Malisetty. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57615 ) Change subject: libpayload: Add support for PCI MMIO CONFIG access. ...................................................................... Patch Set 32: Verified-1 (2 comments) File payloads/libpayload/drivers/qc_pci_mmio_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143140): https://review.coreboot.org/c/coreboot/+/57615/comment/a19fe8d9_fa027237 PS32, Line 107: cfg_address = (void*) pci_mmio_info->config_base; "(foo*)" should be "(foo *)" File payloads/libpayload/include/qc_pci.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143140): https://review.coreboot.org/c/coreboot/+/57615/comment/83c9bf7f_1731644b PS32, Line 70: #endif trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/57615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Gerrit-Change-Number: 57615 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 19:40:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: qualcomm/sc7280: Add support for edp and mdp driver
by Ravi kumar (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Ravi kumar, Sudheer Amrabadi, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61342 to look at the new patch set (#13). Change subject: qualcomm/sc7280: Add support for edp and mdp driver ...................................................................... qualcomm/sc7280: Add support for edp and mdp driver - Add support for edp aux read and write. - Update edp panel properties based on edid read. - Configure edp controller and edp phy. BUG=b:182963902,b:216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Vinod Polimera <quic_vpolimer(a)quicinc.com> Change-Id: If89abb76028766b19450e756889a5d7776106f95 --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/display/edp_aux.c A src/soc/qualcomm/sc7280/display/edp_ctrl.c A src/soc/qualcomm/sc7280/display/edp_phy_7nm.c A src/soc/qualcomm/sc7280/display/mdss.c A src/soc/qualcomm/sc7280/include/soc/display/edp_aux.h A src/soc/qualcomm/sc7280/include/soc/display/edp_ctrl.h A src/soc/qualcomm/sc7280/include/soc/display/edp_phy.h A src/soc/qualcomm/sc7280/include/soc/display/edp_reg.h A src/soc/qualcomm/sc7280/include/soc/display/mdssreg.h 12 files changed, 3,139 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/61342/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/61342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If89abb76028766b19450e756889a5d7776106f95 Gerrit-Change-Number: 61342 Gerrit-PatchSet: 13 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload: Parse DDR information through coreboot tables
by Ravi kumar (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Ravi kumar, Ravi Kumar Bokka, mturney mturney, Angel Pons, Julius Werner, Arthur Heymans, Xixi Chen. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59193 to look at the new patch set (#35). Change subject: libpayload: Parse DDR information through coreboot tables ...................................................................... libpayload: Parse DDR information through coreboot tables BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e --- M payloads/libpayload/include/libpayload.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c A src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 4 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/59193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e Gerrit-Change-Number: 59193 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-CC: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/drivers/wifi: Adding Kconfig for DDRRFIM
by Varshit B Pandya (Code Review) 04 Mar '22

04 Mar '22

Varshit B Pandya has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/61593 ) Change subject: src/drivers/wifi: Adding Kconfig for DDRRFIM ...................................................................... Abandoned redundant -- To view, visit https://review.coreboot.org/c/coreboot/+/61593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6fd991b714add54feb898723bfbfeab63a2e0c Gerrit-Change-Number: 61593 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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