coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/nivviks: Implement WWAN power sequencing
by Eric Lai (Code Review) 09 Mar '22

09 Mar '22

Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61694 ) Change subject: mb/google/brya/var/nivviks: Implement WWAN power sequencing ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: We usually do the WWAN power sequence in coreboot due to WWAN module need time to get ready before kernel can probe it. Not sure FM101 need how much time to init itself. -- To view, visit https://review.coreboot.org/c/coreboot/+/61694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada Gerrit-Change-Number: 61694 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 00:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Hung-Te Lin (Code Review) 09 Mar '22

09 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... soc/mediatek: Add PCIe support Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/Kconfig A src/soc/mediatek/common/include/soc/pcie_common.h A src/soc/mediatek/common/pcie.c 3 files changed, 278 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index 27f6cec..cd3b2a2 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -1,5 +1,6 @@ config SOC_MEDIATEK_COMMON bool + select NO_ECAM_MMCONF_SUPPORT if PCI help common code blocks for Mediatek SOCs diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h new file mode 100644 index 0000000..d737c9d --- /dev/null +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_PCIE_COMMON_H +#define SOC_MEDIATEK_PCIE_COMMON_H + +#include <device/device.h> +#include <types.h> + +struct mtk_pcie_mmio_res { + uint32_t cpu_addr; + uint32_t pci_addr; + uint32_t size; + unsigned long type; +}; + +struct mtk_pcie_controller { + uintptr_t base; /* MAC physical address */ + int (*phy_init)(void); + void (*reset)(uintptr_t base, bool enable); + const struct mtk_pcie_mmio_res *mmio_res_io; + const struct mtk_pcie_mmio_res *mmio_res_mem; +}; + +void mtk_pcie_domain_read_resources(struct device *dev); +void mtk_pcie_domain_set_resources(struct device *dev); +void mtk_pcie_domain_enable(struct device *dev); + +#endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c new file mode 100644 index 0000000..c05db8c --- /dev/null +++ b/src/soc/mediatek/common/pcie.c @@ -0,0 +1,249 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <commonlib/stdlib.h> +#include <console/console.h> +#include <device/device.h> +#include <device/mmio.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/resource.h> +#include <delay.h> +#include <lib.h> +#include <soc/addressmap.h> +#include <soc/pcie.h> +#include <soc/pcie_common.h> +#include <stdlib.h> +#include <types.h> + +#define PCIE_SETTING_REG 0x80 +#define PCIE_PCI_IDS_1 0x9c +#define PCI_CLASS(class) ((class) << 8) +#define PCIE_RC_MODE BIT(0) + +#define PCIE_CFGNUM_REG 0x140 +#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) +#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) +#define PCIE_CFG_OFFSET_ADDR 0x1000 +#define PCIE_CFG_HEADER(bus, devfn) \ + (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) + +#define PCIE_RST_CTRL_REG 0x148 +#define PCIE_MAC_RSTB BIT(0) +#define PCIE_PHY_RSTB BIT(1) +#define PCIE_BRG_RSTB BIT(2) +#define PCIE_PE_RSTB BIT(3) + +#define PCIE_LTSSM_STATUS_REG 0x150 +#define PCIE_LTSSM_STATE(val) (((val) >> 24) & 0x1f) + +#define PCIE_LINK_STATUS_REG 0x154 +#define PCIE_CTRL_LINKUP BIT(8) + +#define PCI_NUM_INTX 4 +#define PCIE_INT_ENABLE_REG 0x180 +#define PCIE_INTX_SHIFT 24 +#define PCIE_INTX_ENABLE \ + GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) + +#define PCIE_TRANS_TABLE_BASE_REG 0x800 +#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 +#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 +#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc +#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 +#define PCIE_ATR_TLB_SET_OFFSET 0x20 + +#define PCIE_MAX_TRANS_TABLES 8 +#define PCIE_ATR_EN BIT(0) +#define PCIE_ATR_SIZE(size) \ + (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) +#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) +#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) +#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) +#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) +#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) +#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) + +static struct mtk_pcie_controller pcie_ctrl; + +/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ +static const char *const ltssm_str[] = { + "detect.quiet", /* 0x00 */ + "detect.active", /* 0x01 */ + "polling.active", /* 0x02 */ + "polling.compliance", /* 0x03 */ + "polling.configuration", /* 0x04 */ + "config.linkwidthstart", /* 0x05 */ + "config.linkwidthaccept", /* 0x06 */ + "config.lanenumwait", /* 0x07 */ + "config.lanenumaccept", /* 0x08 */ + "config.complete", /* 0x09 */ + "config.idle", /* 0x0A */ + "recovery.receiverlock", /* 0x0B */ + "recovery.equalization", /* 0x0C */ + "recovery.speed", /* 0x0D */ + "recovery.receiverconfig", /* 0x0E */ + "recovery.idle", /* 0x0F */ + "L0", /* 0x10 */ + "L0s", /* 0x11 */ + "L1.entry", /* 0x12 */ + "L1.idle", /* 0x13 */ + "L2.idle", /* 0x14 */ + "L2.transmitwake", /* 0x15 */ + "disable", /* 0x16 */ + "loopback.entry", /* 0x17 */ + "loopback.active", /* 0x18 */ + "loopback.exit", /* 0x19 */ + "hotreset", /* 0x1A */ +}; + +volatile union pci_bank *pci_map_bus(pci_devfn_t dev) +{ + u32 val, devfn, bus; + + devfn = PCI_DEV2DEVFN(dev); + bus = PCI_DEV2SEGBUS(dev); + val = PCIE_CFG_HEADER(bus, devfn); + + write32p(pcie_ctrl.base + PCIE_CFGNUM_REG, val); + + return (void *)(pcie_ctrl.base + PCIE_CFG_OFFSET_ADDR); +} + +static int mtk_pcie_startup_port(struct mtk_pcie_controller *ctrl) +{ + uint32_t val; + size_t tries = 0; + const char *ltssm_state; + + /* Set as RC mode */ + val = read32p(ctrl->base + PCIE_SETTING_REG); + val |= PCIE_RC_MODE; + write32p(ctrl->base + PCIE_SETTING_REG, val); + + /* Set class code */ + val = read32p(ctrl->base + PCIE_PCI_IDS_1); + val &= ~GENMASK(31, 8); + val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); + write32p(ctrl->base + PCIE_PCI_IDS_1, val); + + /* Mask all INTx interrupts */ + val = read32p(ctrl->base + PCIE_INT_ENABLE_REG); + val &= ~PCIE_INTX_ENABLE; + write32p(ctrl->base + PCIE_INT_ENABLE_REG, val); + + if (!ctrl->reset) { + printk(BIOS_ERR, "%s: Missing reset function\n", __func__); + return -1; + } + + /* De-assert reset signals */ + ctrl->reset(ctrl->base + PCIE_RST_CTRL_REG, false); + + if (!retry(100, + (tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) & + PCIE_CTRL_LINKUP), mdelay(1))) { + val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG); + ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? + "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; + printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", + __func__, ltssm_state); + return -1; + } + + printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, + tries); + + return 0; +} + +static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, + const struct mtk_pcie_mmio_res *mmio_res) +{ + const char *range_type; + uint32_t table_attr; + + if (!mmio_res) + return -1; + + if (mmio_res->type == IORESOURCE_IO) { + range_type = "IO"; + table_attr = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; + } else if (mmio_res->type == IORESOURCE_MEM) { + range_type = "MEM"; + table_attr = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; + } else { + printk(BIOS_ERR, "%s: Unknown trans table type %#lx\n", + __func__, mmio_res->type); + return -1; + } + + write32p(table, mmio_res->cpu_addr | + PCIE_ATR_SIZE(__fls(mmio_res->size))); + write32p(table + PCIE_ATR_SRC_ADDR_MSB_OFFSET, 0); + write32p(table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET, mmio_res->pci_addr); + write32p(table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET, 0); + write32p(table + PCIE_ATR_TRSL_PARAM_OFFSET, table_attr); + + printk(BIOS_INFO, + "%s: set %s trans window: cpu_addr = %#x, pci_addr = %#x, size = %#x\n", + __func__, range_type, mmio_res->cpu_addr, mmio_res->pci_addr, + mmio_res->size); + + return 0; +} + +static void mtk_pcie_domain_new_res(struct device *dev, unsigned int index, + const struct mtk_pcie_mmio_res *mmio_res) +{ + struct resource *res; + + if (!mmio_res) + return; + + res = new_resource(dev, index); + res->base = mmio_res->cpu_addr; + res->limit = mmio_res->cpu_addr + mmio_res->size - 1; + res->flags = mmio_res->type | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; +} + +void mtk_pcie_domain_read_resources(struct device *dev) +{ + struct mtk_pcie_controller *ctrl = dev->chip_info; + + mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0), + ctrl->mmio_res_io); + + mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0), + ctrl->mmio_res_mem); +} + +void mtk_pcie_domain_set_resources(struct device *dev) +{ + struct mtk_pcie_controller *ctrl = dev->chip_info; + uintptr_t table; + + /* Initialize I/O space constraints. */ + table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG; + if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0) + printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__); + + /* Initialize memory resources constraints. */ + table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG + + PCIE_ATR_TLB_SET_OFFSET; + if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_mem) < 0) + printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__); + + pci_domain_set_resources(dev); +} + +void mtk_pcie_domain_enable(struct device *dev) +{ + mtk_pcie_get_hw_info(&pcie_ctrl); + + if (mtk_pcie_startup_port(&pcie_ctrl) < 0) + return; + + dev->chip_info = &pcie_ctrl; +} 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Fix broken links
by Martin Roth (Code Review) 09 Mar '22

09 Mar '22

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62672 ) Change subject: Documentation: Fix broken links ...................................................................... Documentation: Fix broken links This change just changes some links that were identified as broken by the 'website_scans' jenkins job. There are still lots more to do. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef --- M Documentation/community/code_of_conduct.md M Documentation/community/conferences.md M Documentation/contributing/coding_style.md M Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/f2a85-m.md M Documentation/mainboard/asus/p8h61-m_lx.md 7 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62672/1 diff --git a/Documentation/community/code_of_conduct.md b/Documentation/community/code_of_conduct.md index 249a575..179612c 100644 --- a/Documentation/community/code_of_conduct.md +++ b/Documentation/community/code_of_conduct.md @@ -115,4 +115,4 @@ This Code of Conduct is distributed under a [Creative Commons Attribution-ShareAlike license](http://creativecommons.org/licenses/by-sa/3.0/). It is based -on the [Citizen Code of Conduct](http://citizencodeofconduct.org/) +on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofcon… diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md index dc4a1b9..db89f27 100644 --- a/Documentation/community/conferences.md +++ b/Documentation/community/conferences.md @@ -14,7 +14,7 @@ [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_fa… by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebo…) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03) -[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018) +[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/cong… ([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27) [coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018 diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index e3c92af..6564545 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -966,11 +966,14 @@ The C Programming Language, Second Edition by Brian W. Kernighan and Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8 (paperback), 0-13-110370-9 (hardback). URL: -<http://cm.bell-labs.com/cm/cs/cbook/> +<https://duckduckgo.com/?q=isbn+0-13-110362-8> or +<https://www.google.com/search?q=isbn+0-13-110362-8. + The Practice of Programming by Brian W. Kernighan and Rob Pike. Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL: -<http://cm.bell-labs.com/cm/cs/tpop/> +<https://duckduckgo.com/?q=ISBN+0-201-61586-X> or +<https://www.google.com/search?q=ISBN+0-201-61586-X> GNU manuals - where in compliance with K&R and this text - for cpp, gcc, gcc internals and indent, all available from diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 4d26cfd..3aae1e5 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -131,4 +131,4 @@ [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%… [flashrom]: https://flashrom.org/Flashrom -[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf +[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.… diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 6a0da5b..9d5c288 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -130,4 +130,4 @@ [ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/ [W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf [flashrom]: https://flashrom.org/Flashrom -[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf +[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.… diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md index dfde07f..ce7c2497 100644 --- a/Documentation/mainboard/asus/f2a85-m.md +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -190,9 +190,9 @@ - [Board manual] - Flash chip datasheet [W25Q64FV] -[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/ -[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf +[ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards… +[Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/AS… [flashrom]: https://flashrom.org/Flashrom [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines [TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 -[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource… diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index 212ed97..a4b54cd 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -106,6 +106,6 @@ - [Flash chip datasheet][W25Q32BV] [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/ -[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource… [flashrom]: https://flashrom.org/Flashrom [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip -- To view, visit https://review.coreboot.org/c/coreboot/+/62672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Gerrit-Change-Number: 62672 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/psp_verstage: Log the platform boot mode report
by Rob Barnes (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62668 ) Change subject: soc/amd/cezanne/psp_verstage: Log the platform boot mode report ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Gerrit-Change-Number: 62668 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 00:37:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
by Rob Barnes (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62667 ) Change subject: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb Gerrit-Change-Number: 62667 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 00:36:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Add loglevel marker codes to stored consoles
by Yu-Ping Wu (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61308 ) Change subject: console: Add loglevel marker codes to stored consoles ...................................................................... Patch Set 12: (1 comment) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/61308/comment/c84635cf_1759dc2d PS12, Line 798: coreboot There will be a BIOS_NOTICE marker before "coreboot". -- To view, visit https://review.coreboot.org/c/coreboot/+/61308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc Gerrit-Change-Number: 61308 Gerrit-PatchSet: 12 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 00:27:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: spd/lp5: Add new part MT62F2G32D8DR-031
by Eric Lai (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Amanda Hwang, Ivy Jian, Karthik Ramasubramanian. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 ) Change subject: spd/lp5: Add new part MT62F2G32D8DR-031 ...................................................................... Patch Set 3: (1 comment) File spd/lp5/memory_parts.json: https://review.coreboot.org/c/coreboot/+/62542/comment/a21f6c80_6bbe0d87 PS1, Line 54: "name": "MT62F2G32D8DR-031 WT:B", > Ack. IIUC, there are 2 ways to handle this memory part […] IIRC, AMD and Intel platform can separate the SPD mechanism and create more set. So should be fine if we want to. -- To view, visit https://review.coreboot.org/c/coreboot/+/62542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Gerrit-Change-Number: 62542 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 00:27:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Reka Norman <rekanorman(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
by Karthik Ramasubramanian (Code Review) 08 Mar '22

08 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62387 ) Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ...................................................................... util/spd_tools: Encode SDRAM min cycle time (TCKMinPs) ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle time. Encode tCKMin as per the respective advisories. BUG=None TEST=Generate the SPD and ensure that tCKMin is encoded accordingly. Minimum CAS Latency time is also impacted and is encoded accordingly. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M spd/lp5/set-1/spd-1.hex M spd/lp5/set-1/spd-2.hex M spd/lp5/set-1/spd-3.hex M util/spd_tools/src/spd_gen/lp5.go 4 files changed, 42 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Reka Norman: Looks good to me, approved diff --git a/spd/lp5/set-1/spd-1.hex b/spd/lp5/set-1/spd-1.hex index 0ac396b..ccc9107 100644 --- a/spd/lp5/set-1/spd-1.hex +++ b/spd/lp5/set-1/spd-1.hex @@ -1,11 +1,11 @@ 23 11 13 0E 85 19 95 18 00 40 00 00 02 02 00 00 -00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-2.hex b/spd/lp5/set-1/spd-2.hex index 33da5d7..69a5fb5 100644 --- a/spd/lp5/set-1/spd-2.hex +++ b/spd/lp5/set-1/spd-2.hex @@ -1,11 +1,11 @@ 23 11 13 0E 85 19 B5 18 00 40 00 00 0A 02 00 00 -00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 +00 00 03 00 00 00 00 00 2B 00 90 A8 90 90 06 C0 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/spd/lp5/set-1/spd-3.hex b/spd/lp5/set-1/spd-3.hex index b1893db..8090f06 100644 --- a/spd/lp5/set-1/spd-3.hex +++ b/spd/lp5/set-1/spd-3.hex @@ -1,11 +1,11 @@ 23 11 13 0E 86 21 95 18 00 40 00 00 02 02 00 00 -00 00 0A 00 00 00 00 00 AA 00 90 A8 90 C0 08 60 +00 00 03 00 00 00 00 00 2B 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 B9 00 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/util/spd_tools/src/spd_gen/lp5.go b/util/spd_tools/src/spd_gen/lp5.go index c8bcaf5..060cb2a 100644 --- a/util/spd_tools/src/spd_gen/lp5.go +++ b/util/spd_tools/src/spd_gen/lp5.go @@ -44,7 +44,7 @@ } type LP5SpeedParams struct { - TCKMinPs int + defaultTCKMinPs int MaxCASLatency int } @@ -69,6 +69,7 @@ optionalFeatures byte otherOptionalFeatures byte busWidthEncoding byte + speedToTCKMinPs map[int]int } /* ------------------------------------------------------------------------------------------ */ @@ -194,6 +195,19 @@ * Set to 0x01. */ busWidthEncoding: 0x01, + /* + * TCKMinPs: + * LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are + * related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used. + * For ADL, the MRC expects the tCKmin to encode the CK cycle time. + * tCKmin = 1 / CK rate + * = 1 / (WCK rate / WCK:CK) + * = 1 / (speed grade / 2 / WCK:CK) // "double data rate" + */ + speedToTCKMinPs: map[int]int{ + 6400 : 1250, /* 1 / (6400 / 2 / 4) */ + 5500 : 1455, /* 1 / (5500 / 2 / 4) */ + }, }, 1: { SPDRevision: LP5SPDValueRevision1_1, @@ -346,23 +360,20 @@ /* * TCKMinPs: - * LPDDR5 has two clocks: the command/address clock (CK) and the data clock (WCK). They are - * related by the WCK:CK ratio, which can be either 4:1 or 2:1. On ADL, 4:1 is used. - * For ADL, the MRC expects the tCKmin to encode the CK period. This is calculated as: - * tCKmin = 1 / CK rate - * = 1 / (WCK rate / WCK:CK) - * = 1 / (speed grade / 2 / WCK:CK) // "double data rate" + * Data sheets recommend encoding the the WCK cycle time. + * tCKmin = 1 / WCK rate + * = 1 / (speed grade / 2) // "double data rate" * * MaxCASLatency: * From Table 220 of JESD209-5B, using a 4:1 WCK:CK ratio and Set 0. */ var LP5SpeedMbpsToSPDEncoding = map[int]LP5SpeedParams{ 6400: { - TCKMinPs: 1250, /* 1 / (6400 / 2 / 4) */ + defaultTCKMinPs : 312, /* 1 / (6400 / 2) */ MaxCASLatency: 17, }, 5500: { - TCKMinPs: 1455, /* 1 / (5500 / 2 / 4) */ + defaultTCKMinPs : 363, /* 1 / (5500 / 2) */ MaxCASLatency: 15, }, } @@ -550,6 +561,21 @@ return f.busWidthEncoding } +func LP5GetTCKMinPs(memAttribs *LP5MemAttributes) int { + f, ok := LP5SetInfo[LP5CurrSet] + + if ok == false || f.speedToTCKMinPs == nil { + return LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].defaultTCKMinPs + } + + tCKMinPs, ok := f.speedToTCKMinPs[memAttribs.SpeedMbps] + if ok == false || tCKMinPs == 0 { + fmt.Printf("TCKMinPs not defined for speed %d(Mbps) in LP5Set %d\n", memAttribs.SpeedMbps, LP5CurrSet) + } + + return tCKMinPs +} + func LP5EncodeTCKMin(memAttribs *LP5MemAttributes) byte { return convPsToMtbByte(memAttribs.TCKMinPs) } @@ -608,7 +634,7 @@ func LP5UpdateTCKMin(memAttribs *LP5MemAttributes) { if memAttribs.TCKMinPs == 0 { - memAttribs.TCKMinPs = LP5SpeedMbpsToSPDEncoding[memAttribs.SpeedMbps].TCKMinPs + memAttribs.TCKMinPs = LP5GetTCKMinPs(memAttribs) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26 Gerrit-Change-Number: 62387 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: spd/lp5: Add new part MT62F2G32D8DR-031
by Karthik Ramasubramanian (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Reka Norman, Tim Wawrzynczak, Amanda Hwang, Ivy Jian. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62542 ) Change subject: spd/lp5: Add new part MT62F2G32D8DR-031 ...................................................................... Patch Set 3: (1 comment) File spd/lp5/set-1/spd-4.hex: https://review.coreboot.org/c/coreboot/+/62542/comment/e321d81c_33d09b3a PS3, Line 2: 00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0 Looking at the SPD, it seems you did not regenerate the SPD after rebasing. Can you please regenerate the SPD -- To view, visit https://review.coreboot.org/c/coreboot/+/62542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7 Gerrit-Change-Number: 62542 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 23:46:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: docs/contributing/gsoc: Add project proposal template
by Anastasia Klimchuk (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Felix Singer, Martin Roth, David Hendricks. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62659 ) Change subject: docs/contributing/gsoc: Add project proposal template ...................................................................... Patch Set 4: (1 comment) File Documentation/contributing/gsoc.md: https://review.coreboot.org/c/coreboot/+/62659/comment/6ed30561_05700260 PS4, Line 132: The project proposal What I would think of "project proposal" is what contributors propose, their own ideas. And I think there was a template for that already, I remember with more fields like contact info, background of contrubitor etc? This is idea from community right? So maybe project idea? -- To view, visit https://review.coreboot.org/c/coreboot/+/62659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d565ba4bcd56acb88916b0a93f59121d04fb570 Gerrit-Change-Number: 62659 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 23:40:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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