coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
by Raihow Shi (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: YH Lin, Paul Menzel, Zoey Wu, Felix Held. Raihow Shi has removed Angel Pons from this change. ( https://review.coreboot.org/c/coreboot/+/62374 ) Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A ...................................................................... Removed reviewer Angel Pons. -- To view, visit https://review.coreboot.org/c/coreboot/+/62374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Gerrit-Change-Number: 62374 Gerrit-PatchSet: 10 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Dtrain Hsu (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62553 to look at the new patch set (#9). Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... mb/google/brya/var/kinox: update overridetree 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 193 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 9 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down
by Jianjun Wang (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62673 ) Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Is it a common scenario that PCIe link will go down? Sort of, SSD card broken or not connected will cause PCIe link down, the only common scenario that I can think of is we add the PCIe domain in devicetree.cb, but choose eMMC boot and the SSD card is not connected. -- To view, visit https://review.coreboot.org/c/coreboot/+/62673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387 Gerrit-Change-Number: 62673 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 02:43:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "soc/mediatek: Add PCIe support"
by Yu-Ping Wu (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Nico Huber, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62678 ) Change subject: Revert "soc/mediatek: Add PCIe support" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdc631879e623181894f6c41198a09749725cc47 Gerrit-Change-Number: 62678 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 02:41:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: prog_loader: Change legacy_romstage_select_and_load() to return cb_err
by Yu-Ping Wu (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Julius Werner. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62656 ) Change subject: prog_loader: Change legacy_romstage_select_and_load() to return cb_err ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5510d05953fe8c0e2cb511f01f862b66ced154ae Gerrit-Change-Number: 62656 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 02:41:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Hung-Te Lin (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jianjun Wang. Hung-Te Lin has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: revert

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Change in coreboot[master]: Revert "soc/mediatek: Add PCIe support"
by Hung-Te Lin (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Shelley Chen, Nico Huber, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hello Shelley Chen, build bot (Jenkins), Nico Huber, Angel Pons, Yu-Ping Wu, Jianjun Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62678 to review the following change. Change subject: Revert "soc/mediatek: Add PCIe support" ...................................................................... Revert "soc/mediatek: Add PCIe support" This reverts commit 270b0b60acba4802b8a9272d2727ee576733ad47. Reason for revert: The implementation had a few issues and is not complete. Change-Id: Icdc631879e623181894f6c41198a09749725cc47 --- M src/soc/mediatek/common/Kconfig D src/soc/mediatek/common/include/soc/pcie_common.h D src/soc/mediatek/common/pcie.c 3 files changed, 0 insertions(+), 278 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62678/1 diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index cd3b2a2..27f6cec 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -1,6 +1,5 @@ config SOC_MEDIATEK_COMMON bool - select NO_ECAM_MMCONF_SUPPORT if PCI help common code blocks for Mediatek SOCs diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h deleted file mode 100644 index d737c9d..0000000 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_PCIE_COMMON_H -#define SOC_MEDIATEK_PCIE_COMMON_H - -#include <device/device.h> -#include <types.h> - -struct mtk_pcie_mmio_res { - uint32_t cpu_addr; - uint32_t pci_addr; - uint32_t size; - unsigned long type; -}; - -struct mtk_pcie_controller { - uintptr_t base; /* MAC physical address */ - int (*phy_init)(void); - void (*reset)(uintptr_t base, bool enable); - const struct mtk_pcie_mmio_res *mmio_res_io; - const struct mtk_pcie_mmio_res *mmio_res_mem; -}; - -void mtk_pcie_domain_read_resources(struct device *dev); -void mtk_pcie_domain_set_resources(struct device *dev); -void mtk_pcie_domain_enable(struct device *dev); - -#endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c deleted file mode 100644 index c05db8c..0000000 --- a/src/soc/mediatek/common/pcie.c +++ /dev/null @@ -1,249 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <commonlib/stdlib.h> -#include <console/console.h> -#include <device/device.h> -#include <device/mmio.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/resource.h> -#include <delay.h> -#include <lib.h> -#include <soc/addressmap.h> -#include <soc/pcie.h> -#include <soc/pcie_common.h> -#include <stdlib.h> -#include <types.h> - -#define PCIE_SETTING_REG 0x80 -#define PCIE_PCI_IDS_1 0x9c -#define PCI_CLASS(class) ((class) << 8) -#define PCIE_RC_MODE BIT(0) - -#define PCIE_CFGNUM_REG 0x140 -#define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) -#define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) -#define PCIE_CFG_OFFSET_ADDR 0x1000 -#define PCIE_CFG_HEADER(bus, devfn) \ - (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) - -#define PCIE_RST_CTRL_REG 0x148 -#define PCIE_MAC_RSTB BIT(0) -#define PCIE_PHY_RSTB BIT(1) -#define PCIE_BRG_RSTB BIT(2) -#define PCIE_PE_RSTB BIT(3) - -#define PCIE_LTSSM_STATUS_REG 0x150 -#define PCIE_LTSSM_STATE(val) (((val) >> 24) & 0x1f) - -#define PCIE_LINK_STATUS_REG 0x154 -#define PCIE_CTRL_LINKUP BIT(8) - -#define PCI_NUM_INTX 4 -#define PCIE_INT_ENABLE_REG 0x180 -#define PCIE_INTX_SHIFT 24 -#define PCIE_INTX_ENABLE \ - GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) - -#define PCIE_TRANS_TABLE_BASE_REG 0x800 -#define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 -#define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 -#define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc -#define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 -#define PCIE_ATR_TLB_SET_OFFSET 0x20 - -#define PCIE_MAX_TRANS_TABLES 8 -#define PCIE_ATR_EN BIT(0) -#define PCIE_ATR_SIZE(size) \ - (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) -#define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) -#define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) -#define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) -#define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) -#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) -#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) - -static struct mtk_pcie_controller pcie_ctrl; - -/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ -static const char *const ltssm_str[] = { - "detect.quiet", /* 0x00 */ - "detect.active", /* 0x01 */ - "polling.active", /* 0x02 */ - "polling.compliance", /* 0x03 */ - "polling.configuration", /* 0x04 */ - "config.linkwidthstart", /* 0x05 */ - "config.linkwidthaccept", /* 0x06 */ - "config.lanenumwait", /* 0x07 */ - "config.lanenumaccept", /* 0x08 */ - "config.complete", /* 0x09 */ - "config.idle", /* 0x0A */ - "recovery.receiverlock", /* 0x0B */ - "recovery.equalization", /* 0x0C */ - "recovery.speed", /* 0x0D */ - "recovery.receiverconfig", /* 0x0E */ - "recovery.idle", /* 0x0F */ - "L0", /* 0x10 */ - "L0s", /* 0x11 */ - "L1.entry", /* 0x12 */ - "L1.idle", /* 0x13 */ - "L2.idle", /* 0x14 */ - "L2.transmitwake", /* 0x15 */ - "disable", /* 0x16 */ - "loopback.entry", /* 0x17 */ - "loopback.active", /* 0x18 */ - "loopback.exit", /* 0x19 */ - "hotreset", /* 0x1A */ -}; - -volatile union pci_bank *pci_map_bus(pci_devfn_t dev) -{ - u32 val, devfn, bus; - - devfn = PCI_DEV2DEVFN(dev); - bus = PCI_DEV2SEGBUS(dev); - val = PCIE_CFG_HEADER(bus, devfn); - - write32p(pcie_ctrl.base + PCIE_CFGNUM_REG, val); - - return (void *)(pcie_ctrl.base + PCIE_CFG_OFFSET_ADDR); -} - -static int mtk_pcie_startup_port(struct mtk_pcie_controller *ctrl) -{ - uint32_t val; - size_t tries = 0; - const char *ltssm_state; - - /* Set as RC mode */ - val = read32p(ctrl->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(ctrl->base + PCIE_SETTING_REG, val); - - /* Set class code */ - val = read32p(ctrl->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(ctrl->base + PCIE_PCI_IDS_1, val); - - /* Mask all INTx interrupts */ - val = read32p(ctrl->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(ctrl->base + PCIE_INT_ENABLE_REG, val); - - if (!ctrl->reset) { - printk(BIOS_ERR, "%s: Missing reset function\n", __func__); - return -1; - } - - /* De-assert reset signals */ - ctrl->reset(ctrl->base + PCIE_RST_CTRL_REG, false); - - if (!retry(100, - (tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) & - PCIE_CTRL_LINKUP), mdelay(1))) { - val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG); - ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? - "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; - printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", - __func__, ltssm_state); - return -1; - } - - printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, - tries); - - return 0; -} - -static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, - const struct mtk_pcie_mmio_res *mmio_res) -{ - const char *range_type; - uint32_t table_attr; - - if (!mmio_res) - return -1; - - if (mmio_res->type == IORESOURCE_IO) { - range_type = "IO"; - table_attr = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; - } else if (mmio_res->type == IORESOURCE_MEM) { - range_type = "MEM"; - table_attr = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; - } else { - printk(BIOS_ERR, "%s: Unknown trans table type %#lx\n", - __func__, mmio_res->type); - return -1; - } - - write32p(table, mmio_res->cpu_addr | - PCIE_ATR_SIZE(__fls(mmio_res->size))); - write32p(table + PCIE_ATR_SRC_ADDR_MSB_OFFSET, 0); - write32p(table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET, mmio_res->pci_addr); - write32p(table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET, 0); - write32p(table + PCIE_ATR_TRSL_PARAM_OFFSET, table_attr); - - printk(BIOS_INFO, - "%s: set %s trans window: cpu_addr = %#x, pci_addr = %#x, size = %#x\n", - __func__, range_type, mmio_res->cpu_addr, mmio_res->pci_addr, - mmio_res->size); - - return 0; -} - -static void mtk_pcie_domain_new_res(struct device *dev, unsigned int index, - const struct mtk_pcie_mmio_res *mmio_res) -{ - struct resource *res; - - if (!mmio_res) - return; - - res = new_resource(dev, index); - res->base = mmio_res->cpu_addr; - res->limit = mmio_res->cpu_addr + mmio_res->size - 1; - res->flags = mmio_res->type | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED; -} - -void mtk_pcie_domain_read_resources(struct device *dev) -{ - struct mtk_pcie_controller *ctrl = dev->chip_info; - - mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0), - ctrl->mmio_res_io); - - mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0), - ctrl->mmio_res_mem); -} - -void mtk_pcie_domain_set_resources(struct device *dev) -{ - struct mtk_pcie_controller *ctrl = dev->chip_info; - uintptr_t table; - - /* Initialize I/O space constraints. */ - table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0) - printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__); - - /* Initialize memory resources constraints. */ - table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG + - PCIE_ATR_TLB_SET_OFFSET; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_mem) < 0) - printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__); - - pci_domain_set_resources(dev); -} - -void mtk_pcie_domain_enable(struct device *dev) -{ - mtk_pcie_get_hw_info(&pcie_ctrl); - - if (mtk_pcie_startup_port(&pcie_ctrl) < 0) - return; - - dev->chip_info = &pcie_ctrl; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdc631879e623181894f6c41198a09749725cc47 Gerrit-Change-Number: 62678 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Yu-Ping Wu (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 21: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/947c5e28_6b62ed9d PS21, Line 248: dev->chip_info = &pcie_ctrl; Also, I don't think we should set chip_info in the code. It should be set in devicetree.cb instead. For example see - mainboard/google/octopus/variants/baseboard/devicetree.cb - soc_intel_apollolake_config in soc/intel/apollolake/chip.h As a result, 'base', 'mmio_res_io' and 'mmio_res_mem' in mtk_pcie_controller should be defined in devicetree. As for ctrl->reset, we can call mtk_pcie_reset() directly (need to add it to a header file so that each SoC can implement its own version). -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 02:36:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down
by Hung-Te Lin (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62673 ) Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Is it a common scenario that PCIe link will go down? -- To view, visit https://review.coreboot.org/c/coreboot/+/62673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387 Gerrit-Change-Number: 62673 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 02:33:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Clear struct match before regular expression matching
by Bao Zheng (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Nikolai Vyssotski, Rob Barnes, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Nikolai Vyssotski, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, Karthikeyan Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62482 to look at the new patch set (#10). Change subject: amdfwtool: Clear struct match before regular expression matching ...................................................................... amdfwtool: Clear struct match before regular expression matching If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/data_parse.c 1 file changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/62482/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Gerrit-Change-Number: 62482 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <karthikmit2005(a)gmail.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Karthikeyan Ramasubramanian <karthikmit2005(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022