Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61694 )
Change subject: mb/google/brya/var/nivviks: Implement WWAN power sequencing
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Thanks for the info. […]
And the FM101 init time is still TBD on the datasheet, but we're guessing it will be similar to L850, i.e. somewhere on the order of 10s.
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Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61694 )
Change subject: mb/google/brya/var/nivviks: Implement WWAN power sequencing
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> We usually do the WWAN power sequence in coreboot due to WWAN module need time to get ready before k […]
Thanks for the info. We haven't tested the WWAN yet since it's lower priority than other things right now. If it doesn't work, I'll try moving the power sequencing to coreboot.
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Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 4: Code-Review+1
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Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
Patch Set 4:
(1 comment)
File spd/lp5/set-1/spd-4.hex:
https://review.coreboot.org/c/coreboot/+/62542/comment/a0c4b659_151bee83
PS3, Line 2: 00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
> Looking at the SPD, it seems you did not regenerate the SPD after rebasing. […]
I have uploaded patch set 4 to regenerate the SPD, thanks.
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Mars Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62642 )
Change subject: mb/google/trogdor: Add variant Gelarshie
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62642/comment/7e380580_f2e9b53e
PS1, Line 7: Add new configs gelarshie
> > Add variant Gelarshie
Done
https://review.coreboot.org/c/coreboot/+/62642/comment/d93c60a8_a3b2a293
PS1, Line 9: boards
> board
Done
File src/mainboard/google/trogdor/Kconfig:
https://review.coreboot.org/c/coreboot/+/62642/comment/4a457885_418d5f5d
PS1, Line 10: TROGDOR_HAS_BRIDGE_BACKLIGHT
> Actually, are you sure about setting this one to "Y"? I believe Homestar set this to `y` because it […]
Thanks for your review, Because display design of Gelarshie same as coachz , I had removed the line.
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Hello Reka Norman, build bot (Jenkins), Jon Murphy, Tim Wawrzynczak, Ivy Jian, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62542
to look at the new patch set (#4).
Change subject: spd/lp5: Add new part MT62F2G32D8DR-031
......................................................................
spd/lp5: Add new part MT62F2G32D8DR-031
Micron MT62F2G32D8DR-031 will be used for skyrim P1. Add it to the parts
list and regenerate the SPDs using spd_gen.
BUG=b:213926260
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Change-Id: Iad2bb53de2b54648d5dd66808973f26b1c8a5df7
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M spd/lp5/memory_parts.json
M spd/lp5/set-0/parts_spd_manifest.generated.txt
A spd/lp5/set-0/spd-4.hex
M spd/lp5/set-1/parts_spd_manifest.generated.txt
A spd/lp5/set-1/spd-4.hex
5 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62542/4
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Jianjun Wang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62673 )
Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down
......................................................................
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Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62553 )
Change subject: mb/google/brya/var/kinox: update overridetree
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/brya/variants/kinox/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62553/comment/90bf9b3f_37309ac7
PS8, Line 52: register "led_feature" = "0xe0"
: register "customized_led0" = "0x23f"
: register "customized_led2" = "0x028"
> Sorry I know this is not very clear, but I believe the 8111 uses the […]
Thanks for review.
Refer to the setting of puff https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… and modify for RTL8111
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