coreboot-gerrit March 2022

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Change in coreboot[master]: mb/siemens/mc_ehl: Use 512 bytes for SPD buffer
by Werner Zeh (Code Review) 09 Mar '22

09 Mar '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Use 512 bytes for SPD buffer ...................................................................... mb/siemens/mc_ehl: Use 512 bytes for SPD buffer DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62698/1 diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 82e2090..c5f906f 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -10,11 +10,13 @@ #include <string.h> #include <types.h> +#include <lib.h> + void mainboard_memory_init_params(FSPM_UPD *memupd) { static struct spd_info spd_info; const struct mb_cfg *board_cfg = variant_memcfg_config(); - static uint8_t spd_data[0x100]; + static uint8_t spd_data[0x200]; const char *cbfs_hwi_name = "hwinfo.hex"; /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to @@ -23,6 +25,7 @@ if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + hexdump(spd_data, sizeof(spd_data)); spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data); spd_info.read_type = READ_SPD_MEMPTR; -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Ronak Kanabar, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61498 ) Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 07:59:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs/merlin: Make ITE files dependant on Kconfig
by Sean Rhodes (Code Review) 09 Mar '22

09 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62677 ) Change subject: ec/starlabs/merlin: Make ITE files dependant on Kconfig ...................................................................... ec/starlabs/merlin: Make ITE files dependant on Kconfig Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 --- M src/ec/starlabs/merlin/Makefile.inc R src/ec/starlabs/merlin/ite.c R src/ec/starlabs/merlin/ite.h 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/62677/1 diff --git a/src/ec/starlabs/merlin/Makefile.inc b/src/ec/starlabs/merlin/Makefile.inc index e6721f5..3445ef3 100644 --- a/src/ec/starlabs/merlin/Makefile.inc +++ b/src/ec/starlabs/merlin/Makefile.inc @@ -8,7 +8,7 @@ EC_VARIANT_DIR := $(call strip_quotes, $(CONFIG_EC_VARIANT_DIR)) CPPFLAGS_common += -I$(src)/ec/starlabs/merlin/variants/$(EC_VARIANT_DIR) -all-y += ec.c +all-y += ite.c ifeq ($(CONFIG_EC_STARLABS_NEED_ITE_BIN),y) ifeq ($(CONFIG_EC_STARLABS_ADD_ITE_BIN),y) diff --git a/src/ec/starlabs/merlin/ec.c b/src/ec/starlabs/merlin/ite.c similarity index 99% rename from src/ec/starlabs/merlin/ec.c rename to src/ec/starlabs/merlin/ite.c index e8eaa22..ef317a9 100644 --- a/src/ec/starlabs/merlin/ec.c +++ b/src/ec/starlabs/merlin/ite.c @@ -7,7 +7,7 @@ #include <option.h> #include <pc80/keyboard.h> -#include "ec.h" +#include "ite.h" #include "ecdefs.h" uint16_t it_get_version(void) diff --git a/src/ec/starlabs/merlin/ec.h b/src/ec/starlabs/merlin/ite.h similarity index 100% rename from src/ec/starlabs/merlin/ec.h rename to src/ec/starlabs/merlin/ite.h -- To view, visit https://review.coreboot.org/c/coreboot/+/62677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5 Gerrit-Change-Number: 62677 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Ronak Kanabar (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Subrata Banik, Andrey Petrov, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61498 ) Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Patch Set 4: (1 comment) File src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: https://review.coreboot.org/c/coreboot/+/61498/comment/30af2611_7e21cb16 PS3, Line 100: BIOS_DEBUG > Can you please change this to BIOS_ERROR? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 07:55:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Ronak Kanabar, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61498 ) Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c: https://review.coreboot.org/c/coreboot/+/61498/comment/8c3bd432_5ea26a7c PS3, Line 100: BIOS_DEBUG Can you please change this to BIOS_ERROR? -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 07:42:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
by Raihow Shi (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Paul Menzel, Angel Pons, Zoey Wu, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62374 ) Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/variants/moli/ramstage.c: https://review.coreboot.org/c/coreboot/+/62374/comment/4489507f_8e01a0c8 PS9, Line 13: PCI_DEVICE_ID_INTEL_ADL_P_ID_10 > Good eye, thanks Felix! I refer to pci_ids.h in CB:39331 and modify it from PCI_DEVICE_ID_INTEL_ADL_P_ID to PCI_DID_INTEL_ADL_P_ID,and local build pass,but robot build fail. -- To view, visit https://review.coreboot.org/c/coreboot/+/62374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99 Gerrit-Change-Number: 62374 Gerrit-PatchSet: 12 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 09 Mar 2022 07:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: {drivers/security}: Replace `cb_err_t` with `enum cb_err`
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62676 ) Change subject: {drivers/security}: Replace `cb_err_t` with `enum cb_err` ...................................................................... {drivers/security}: Replace `cb_err_t` with `enum cb_err` This patch replaces remaining `cb_err_t` with `enum cb_err` after commit hash 69cc557c (commonlib/bsd: Remove cb_err_t) removes majority of `cb_err_t` instances. TEST=Able to build the brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 --- M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h M src/security/tpm/tis.h 5 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/62676/1 diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f8548a7..ce2278b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -514,12 +514,12 @@ { } -cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) +enum cb_err tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) { return cr50_i2c_write(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; } -cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +enum cb_err tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) { return cr50_i2c_read(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 53b3a25..43fd933 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -728,12 +728,12 @@ return payload_size; } -cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) +enum cb_err tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) { return tpm2_write_reg(addr, buffer, bytes); } -cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +enum cb_err tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) { return tpm2_read_reg(addr, buffer, bytes); } diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c index 4b5e813..f96e174 100644 --- a/src/drivers/tpm/cr50.c +++ b/src/drivers/tpm/cr50.c @@ -79,7 +79,7 @@ if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) return 0; - const cb_err_t ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, + const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); if (ret != CB_SUCCESS) { printk(BIOS_INFO, "Error reading from cr50\n"); @@ -92,10 +92,10 @@ /** * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. */ -cb_err_t cr50_set_board_cfg(void) +enum cb_err cr50_set_board_cfg(void) { uint32_t value; - cb_err_t ret; + enum cb_err ret; if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) return CB_ERR; @@ -139,7 +139,7 @@ return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); } -static cb_err_t cr50_parse_fw_version(const char *version_str, +static enum cb_err cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) { int epoch, major, minor; @@ -165,7 +165,7 @@ return CB_SUCCESS; } -cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version) +enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version) { if (cr50_firmware_version.epoch || cr50_firmware_version.major || cr50_firmware_version.minor) diff --git a/src/drivers/tpm/cr50.h b/src/drivers/tpm/cr50.h index 4fdd06b..f754e13 100644 --- a/src/drivers/tpm/cr50.h +++ b/src/drivers/tpm/cr50.h @@ -16,9 +16,9 @@ bool cr50_is_long_interrupt_pulse_enabled(void); /* Get the Cr50 firmware version information. */ -cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version); +enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version); /* Set the BOARD_CFG register depending on Cr50 Kconfigs */ -cb_err_t cr50_set_board_cfg(void); +enum cb_err cr50_set_board_cfg(void); #endif /* __DRIVERS_TPM_CR50_H__ */ diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index 0ef5a8a..660ec81 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -96,7 +96,7 @@ * * Returns CB_SUCCESS 0 on success, CB_ERR on failure. */ -cb_err_t tis_vendor_write(unsigned int addr, const void *sendbuf, size_t send_size); +enum cb_err tis_vendor_write(unsigned int addr, const void *sendbuf, size_t send_size); /* * tis_vendor_read() @@ -109,7 +109,7 @@ * * Returns CB_SUCCESS on success or -1 on failure. */ -cb_err_t tis_vendor_read(unsigned int addr, void *recvbuf, size_t recv_size); +enum cb_err tis_vendor_read(unsigned int addr, void *recvbuf, size_t recv_size); static inline bool tpm_first_access_this_boot(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Gerrit-Change-Number: 62676 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Ronak Kanabar (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Subrata Banik, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61498 to look at the new patch set (#3). Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" This reverts commit 6af980a2aeca9b8cedfb3d7734389e6e36099c88. BUG=b:199246420 Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 3 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/61498/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Enable pen garage
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Kangheui Won, Reka Norman, Tim Wawrzynczak, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62675 ) Change subject: mb/google/nissa/var/nivviks: Enable pen garage ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Gerrit-Change-Number: 62675 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 06:31:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/nivviks: Implement WWAN power sequencing
by Eric Lai (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Reka Norman. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61694 ) Change subject: mb/google/brya/var/nivviks: Implement WWAN power sequencing ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/nivviks/overridetree.cb: https://review.coreboot.org/c/coreboot/+/61694/comment/29a65622_b4504176 PS3, Line 288: register "enable_delay_ms" = "20" after check the FM101 spec, we need enable_off_delay_ms 100 here. -- To view, visit https://review.coreboot.org/c/coreboot/+/61694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada Gerrit-Change-Number: 61694 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 06:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022