coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run se...
by Maulik V Vaghela (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Ronak Kanabar, Andrey Petrov, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61498 ) Change subject: Revert "drivers/intel/fsp2_0: Allow `mp_startup_all_cpus()` to run serially" ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb7aa6d52b563485a496798f2fe31ed64b4f4a8 Gerrit-Change-Number: 61498 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 09:13:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/common/block/cse: Add option to send EOP early via SoC
by Ronak Kanabar (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Patrick Rudolph. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60195 ) Change subject: intel/common/block/cse: Add option to send EOP early via SoC ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/60195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Gerrit-Change-Number: 60195 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 09:11:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Ronak Kanabar (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 09:11:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/starlabs/lite: Add Lite Mk IV variant
by Sean Rhodes (Code Review) 09 Mar '22

09 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62706 ) Change subject: mb/starlabs/lite: Add Lite Mk IV variant ...................................................................... mb/starlabs/lite: Add Lite Mk IV variant Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f --- M src/mainboard/starlabs/lite/Kconfig M src/mainboard/starlabs/lite/Kconfig.name A src/mainboard/starlabs/lite/variants/glkr/Makefile.inc A src/mainboard/starlabs/lite/variants/glkr/data.vbt A src/mainboard/starlabs/lite/variants/glkr/devicetree.cb A src/mainboard/starlabs/lite/variants/glkr/gpio.c A src/mainboard/starlabs/lite/variants/glkr/romstage.c 7 files changed, 858 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/62706/1 diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig index de2e8e1..9909eae 100644 --- a/src/mainboard/starlabs/lite/Kconfig +++ b/src/mainboard/starlabs/lite/Kconfig @@ -2,7 +2,6 @@ def_bool n select BOARD_ROMSIZE_KB_8192 select DRIVERS_I2C_HID - select EC_STARLABS_ITE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -20,6 +19,13 @@ config BOARD_STARLABS_LITE_GLK select BOARD_STARLABS_LITE_SERIES + select EC_STARLABS_ITE + select EC_STARLABS_KBL_LEVELS + select SOC_INTEL_GEMINILAKE + +config BOARD_STARLABS_LITE_GLKR + select BOARD_STARLABS_LITE_SERIES + select EC_STARLABS_NUVOTON select EC_STARLABS_KBL_LEVELS select SOC_INTEL_GEMINILAKE @@ -32,7 +38,8 @@ default 0x26 config EC_VARIANT_DIR - default "glk" + default "glk" if BOARD_STARLABS_LITE_GLK + default "glkr" if BOARD_STARLABS_LITE_GLKR config FMDFILE default "src/mainboard/starlabs/lite/board.fmd" @@ -42,10 +49,12 @@ config MAINBOARD_FAMILY string - default "I3" + default "I3" if BOARD_STARLABS_LITE_GLK + default "I4" if BOARD_STARLABS_LITE_GLKR config MAINBOARD_PART_NUMBER - default "Lite Mk III" + default "Lite Mk III" if BOARD_STARLABS_LITE_GLK + default "Lite Mk IV" if BOARD_STARLABS_LITE_GLKR config MAINBOARD_SMBIOS_PRODUCT_NAME string @@ -63,5 +72,6 @@ default 2 config VARIANT_DIR - default "glk" + default "glk" if BOARD_STARLABS_LITE_GLK + default "glkr" if BOARD_STARLABS_LITE_GLKR endif diff --git a/src/mainboard/starlabs/lite/Kconfig.name b/src/mainboard/starlabs/lite/Kconfig.name index 7cfb612..1046c97 100644 --- a/src/mainboard/starlabs/lite/Kconfig.name +++ b/src/mainboard/starlabs/lite/Kconfig.name @@ -2,3 +2,6 @@ config BOARD_STARLABS_LITE_GLK bool "Star Labs Lite Mk III (N5000)" + +config BOARD_STARLABS_LITE_GLKR + bool "Star Labs Lite Mk IV (N5030)" diff --git a/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc b/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc new file mode 100644 index 0000000..05b0677 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glkr/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +romstage-y += romstage.c diff --git a/src/mainboard/starlabs/lite/variants/glkr/data.vbt b/src/mainboard/starlabs/lite/variants/glkr/data.vbt new file mode 100644 index 0000000..6b6e360 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glkr/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb new file mode 100644 index 0000000..9fbecad --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -0,0 +1,160 @@ +chip soc/intel/apollolake + device cpu_cluster 0 on + device lapic 0 on end + end + + # Graphics + # TODO: + # register "panel_cfg" = "{ + # .up_delay_ms = 0, // T3 + # .backlight_on_delay_ms = 0, // T7 + # .backlight_off_delay_ms = 0, // T9 + # .down_delay_ms = 0, // T10 + # .cycle_delay_ms = 500, // T12 + # .backlight_pwm_hz = 200, // PWM + # }" + +# PM Util (soc/intel/apollolake/pmutil.c) + # Enable the correct decode ranges on the LPC bus. + register "lpc_ioe" = "LPC_IOE_EC_4E_4F | + LPC_IOE_EC_62_66 | + LPC_IOE_KBC_60_64" + + register "dptf_enable" = "0" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + register "pnp_settings" = "PNP_PERF_POWER" + + register "ModPhyIfValue" = "0x12" + + register "usb_config_override" = "1" + register "DisableComplianceMode" = "1" + + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + register "pcie_rp_deemphasis_enable[0]" = "1" + register "pcie_rp_deemphasis_enable[1]" = "1" + register "pcie_rp_deemphasis_enable[2]" = "1" + register "pcie_rp_deemphasis_enable[3]" = "1" + register "pcie_rp_deemphasis_enable[4]" = "1" + register "pcie_rp_deemphasis_enable[5]" = "1" + + # GPE configuration + register "gpe0_dw1" = "PMC_GPE_NW_63_32" + register "gpe0_dw2" = "PMC_GPE_N_95_64" + register "gpe0_dw3" = "PMC_GPE_NW_31_0" + + register "slp_s3_assertion_width_usecs" = "50000" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 00.1 on end # DPTF + device pci 00.2 off end # NPK + device pci 02.0 on end # Gen + device pci 03.0 off end # Iunit + device pci 0c.0 on # CNVi + chip drivers/wifi/generic + register "wake" = "GPE0A_CNVI_PME_STS" + device generic 0 on end + end + end + device pci 0d.0 off end # P2SB + device pci 0d.1 hidden end # PMC + device pci 0d.2 on end # SPI + device pci 0d.3 off end # Shared SRAM + device pci 0e.0 on # Audio + subsystemid 0x10ec 0x111e + end + device pci 0f.0 on end # Heci1 + device pci 0f.1 on end # Heci2 + device pci 0f.2 on end # Heci3 + device pci 11.0 off end # ISH + device pci 12.0 on end # SATA + device pci 13.0 off end # PCIe-A 0 Slot 1 + device pci 13.1 off end # PCIe-A 1 + device pci 13.2 off end # PCIe-A 2 Onboard Lan + device pci 13.3 off end # PCIe-A 3 + device pci 14.0 off end # PCIe-B 0 Slot2 + device pci 14.1 off end # PCIe-B 1 Onboard M2 Slot(Wifi/BT) + device pci 15.0 on # XHCI + ### USB 2.0 Devices + # Motherboard USB Type C + register "usb2_port[0]" = "PORT_EN(OC0)" + # Motherboard USB 3.0 + register "usb2_port[3]" = "PORT_EN(OC0)" + # Internal Webcam + register "usb2_port[4]" = "PORT_EN(OC0)" + # Daughterboard USB 3.0 + register "usb2_port[5]" = "PORT_EN(OC0)" + # Daughterboard SD Card + register "usb2_port[6]" = "PORT_EN(OC0)" + + ### USB 3.0 Devices + # Motherboard USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + # Motherboard USB Type C + register "usb3_port[1]" = "PORT_EN(OC0)" + # Daughterboard USB 3.0 + register "usb3_port[2]" = "PORT_EN(OC0)" + end device pci 15.1 off end # XDCI + device pci 16.0 off end # I2C0 + device pci 16.1 off end # I2C1 + device pci 16.2 off end # I2C2 + device pci 16.3 off end # I2C3 + device pci 17.0 on end # I2C4 + device pci 17.1 off end # I2C5 + device pci 17.2 off end # I2C6 + device pci 17.3 on # I2C7 + # Handled by touchpad.asl + end + device pci 18.0 on end # UART #0 + device pci 18.1 off end # UART #1 + device pci 18.2 on end # UART #2 + device pci 18.3 off end # UART #3 + device pci 19.0 off end # SPI #0 + device pci 19.1 off end # SPI #1 + device pci 19.2 on end # SPI #2 + device pci 1a.0 off end # PWM + device pci 1b.0 off end # SDCard + device pci 1c.0 off end # eMMC + device pci 1e.0 off end # SDIO + device pci 1f.0 on # LPC Interface + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device pci 1f.1 off end # SMBus + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/starlabs/lite/variants/glkr/gpio.c b/src/mainboard/starlabs/lite/variants/glkr/gpio.c new file mode 100644 index 0000000..0bda6ea --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glkr/gpio.c @@ -0,0 +1,544 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> +#include <variants.h> +#include <types.h> + +/* Early pad configuration in bootblock. */ +const struct pad_config early_gpio_table[] = { + /* GPIO_64: UART2_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + /* GPIO_65: UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* ------- GPIO Group NorthWest ------- */ + /* GPIO_0: XDP_H_TCK */ + PAD_NC(GPIO_0, DN_20K), + /* GPIO_1: XDP_H_TRST_N */ + PAD_NC(GPIO_1, DN_20K), + /* GPIO_2: XDP_H_TMS */ + PAD_NC(GPIO_2, DN_20K), + /* GPIO_3: XDP_H_TDI */ + PAD_NC(GPIO_3, DN_20K), + /* GPIO_4: XDP_H_TDO */ + PAD_NC(GPIO_4, DN_20K), + /* GPIO_5: Not Connected */ + PAD_NC(GPIO_5, DN_20K), + /* GPIO_6: XDP_H_PREQ_N */ + PAD_NC(GPIO_6, DN_20K), + /* GPIO_7: XDP_H_PRDY_N */ + PAD_NC(GPIO_7, DN_20K), + /* GPIO_8: Not Connected */ + PAD_NC(GPIO_8, DN_20K), + /* GPIO_9: Not Connected */ + PAD_NC(GPIO_9, DN_20K), + /* GPIO_10: Not Connected */ + PAD_NC(GPIO_10, DN_20K), + /* GPIO_11: Not Connected */ + PAD_NC(GPIO_11, DN_20K), + /* GPIO_12: Not Connected */ + PAD_NC(GPIO_12, DN_20K), + /* GPIO_13: ACCEL1_INT */ + PAD_NC(GPIO_13, DN_20K), + /* GPIO_14: ACCEL2_INT */ + PAD_NC(GPIO_14, DN_20K), + /* GPIO_15: Not Connected */ + PAD_NC(GPIO_15, DN_20K), + /* GPIO_16: SATA_DEVSLP */ + _PAD_CFG_STRUCT(GPIO_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + /* GPIO_17: Not Connected */ + PAD_NC(GPIO_17, DN_20K), + /* GPIO_18: Not Connected */ + PAD_NC(GPIO_18, DN_20K), + /* GPIO_19: PMIC_IRQ# */ + _PAD_CFG_STRUCT(GPIO_19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | + PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)), + /* GPIO_20: Not Connected */ + PAD_NC(GPIO_20, DN_20K), + /* GPIO_21: WLAN_WWAN_COEX3 */ + PAD_NC(GPIO_21, DN_20K), + /* GPIO_22: WLAN_WWAN_COEX3 */ + PAD_NC(GPIO_22, DN_20K), + /* GPIO_23: WLAN_WWAN_COEX3 */ + PAD_NC(GPIO_23, DN_20K), + /* GPIO_24: Not Connected */ + PAD_NC(GPIO_24, DN_20K), + /* GPIO_25: Not Connected */ + PAD_NC(GPIO_25, DN_20K), + /* GPIO_26: TPNL_INT# */ + PAD_NC(GPIO_26, DN_20K), + /* GPIO_27: GPIO_27 */ + PAD_NC(GPIO_27, DN_20K), + /* GPIO_28: GPIO_28 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, ENPD), + /* GPIO_29: Not Connected */ + PAD_NC(GPIO_29, DN_20K), + /* GPIO_30: Not Connected */ + PAD_NC(GPIO_30, DN_20K), + /* GPIO_31: Not Connected */ + PAD_NC(GPIO_31, DN_20K), + /* GPIO_32: Not Connected */ + PAD_NC(GPIO_32, DN_20K), + /* GPIO_33: BT_ON_SOC */ + _PAD_CFG_STRUCT(GPIO_33, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | + PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | + PAD_IOSSTATE(IGNORE)), + /* GPIO_33: WIFI_ON_SOC */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_34, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_35: Not Connected */ + PAD_NC(GPIO_35, DN_20K), + /* GPIO_36: Not Connected */ + PAD_NC(GPIO_36, DN_20K), + /* GPIO_37: Not Connected */ + PAD_NC(GPIO_37, DN_20K), + /* GPIO_38: WAKE_SCI# */ + _PAD_CFG_STRUCT(GPIO_38, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | + PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_39: FP_RST# */ + PAD_NC(GPIO_39, DN_20K), + /* GPIO_40: Not Connected */ + PAD_NC(GPIO_40, DN_20K), + /* GPIO_41: Not Connected */ + PAD_NC(GPIO_41, DN_20K), + /* GPIO_42: SECURITY_FLASH */ + _PAD_CFG_STRUCT(GPIO_42, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + /* GPIO_43: GPIO_43 */ + _PAD_CFG_STRUCT(GPIO_43, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + /* GPIO_44: GPIO_44 */ + _PAD_CFG_STRUCT(GPIO_44, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)), + /* GPIO_45: GPIO_45 */ + _PAD_CFG_STRUCT(GPIO_45, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)), + /* GPIO_46: Not Connected */ + PAD_NC(GPIO_46, DN_20K), + /* GPIO_47: Not Connected */ + PAD_NC(GPIO_47, DN_20K), + /* GPIO_48: PMIC_I2C_SDA */ + _PAD_CFG_STRUCT(GPIO_48, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_49: PMIC_I2C_SCL */ + _PAD_CFG_STRUCT(GPIO_49, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_50: Not Connected */ + PAD_NC(GPIO_50, DN_20K), + /* GPIO_51: Not Connected */ + PAD_NC(GPIO_51, DN_20K), + /* GPIO_52: Not Connected */ + PAD_NC(GPIO_52, DN_20K), + /* GPIO_53: Not Connected */ + PAD_NC(GPIO_53, DN_20K), + /* GPIO_54: Not Connected */ + PAD_NC(GPIO_54, DN_20K), + /* GPIO_55: Not Connected */ + PAD_NC(GPIO_55, DN_20K), + /* GPIO_56: I2C_SDA_GS */ + _PAD_CFG_STRUCT(GPIO_56, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_57: I2C_SCL_GS */ + _PAD_CFG_STRUCT(GPIO_57, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_58: I2C4_SDA */ + _PAD_CFG_STRUCT(GPIO_58, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_59: I2C4_SCL */ + _PAD_CFG_STRUCT(GPIO_59, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_60: GPIO_60 */ + PAD_NC(GPIO_60, DN_20K), + /* GPIO_61: GPIO_61 */ + _PAD_CFG_STRUCT(GPIO_61, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K)), + /* GPIO_62: Not Connected */ + PAD_NC(GPIO_62, DN_20K), + /* GPIO_63: Not Connected */ + PAD_NC(GPIO_63, DN_20K), + /* GPIO_66: GPIO_66 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_67: SMC_EXTSMI# */ + _PAD_CFG_STRUCT(GPIO_67, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | + (1 << 1), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_68: Not Connected */ + PAD_NC(GPIO_68, DN_20K), + /* GPIO_69: Not Connected */ + PAD_NC(GPIO_69, DN_20K), + /* GPIO_70: Not Connected */ + PAD_NC(GPIO_70, DN_20K), + /* GPIO_71: Not Connected */ + PAD_NC(GPIO_71, DN_20K), + /* GPIO_72: Not Connected */ + PAD_NC(GPIO_72, DN_20K), + /* GPIO_73: Not Connected */ + PAD_NC(GPIO_73, DN_20K), + /* GPIO_74: PMIC_THERMTRIP# */ + _PAD_CFG_STRUCT(GPIO_74, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_75: PROCHOT#_CPU */ + _PAD_CFG_STRUCT(GPIO_75, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + /* GPIO_211: EMMC_RST#_CPU */ + PAD_NC(GPIO_211, DN_20K), + /* GPIO_212: BRD_ID_0 */ + PAD_NC(GPIO_212, DN_20K), + /* GPIO_213: BRD_ID_1 */ + PAD_NC(GPIO_213, DN_20K), + /* GPIO_214: BRD_ID_2 */ + PAD_NC(GPIO_214, DN_20K), + + /* ------- GPIO Group North ------- */ + /* GPIO_76: Not Connected */ + PAD_NC(GPIO_76, DN_20K), + /* GPIO_77: Not Connected */ + PAD_NC(GPIO_77, DN_20K), + /* GPIO_78: Not Connected */ + PAD_NC(GPIO_78, DN_20K), + /* GPIO_79: GPIO_79 */ + _PAD_CFG_STRUCT(GPIO_79, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)), + /* GPIO_80: FP_FS0 */ + PAD_NC(GPIO_80, DN_20K), + /* GPIO_81: GPIO_81 */ + _PAD_CFG_STRUCT(GPIO_81, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)), + /* GPIO_82: FP_MISO */ + PAD_NC(GPIO_82, DN_20K), + /* GPIO_83: GPIO_83 */ + _PAD_CFG_STRUCT(GPIO_83, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD)), + /* GPIO_84: GPIO_84 */ + PAD_CFG_GPI_TRIG_OWN(GPIO_84, DN_20K, DEEP, OFF, ACPI), + /* GPIO_85: Not Connected */ + PAD_NC(GPIO_85, DN_20K), + /* GPIO_86: GPIO_86 */ + _PAD_CFG_STRUCT(GPIO_86, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K)), + /* GPIO_87: Not Connected */ + PAD_NC(GPIO_87, DN_20K), + /* GPIO_88: Not Connected */ + PAD_NC(GPIO_88, DN_20K), + /* GPIO_89: Not Connected */ + PAD_NC(GPIO_89, DN_20K), + /* GPIO_90: FLASH_SPI_CS0_N */ + _PAD_CFG_STRUCT(GPIO_90, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + /* GPIO_91: Not Connected */ + PAD_NC(GPIO_91, DN_20K), + /* GPIO_91: FLASH_SPI_MOSI */ + _PAD_CFG_STRUCT(GPIO_92, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE), PAD_PULL(NATIVE)), + /* GPIO_92: FLASH_SPI_MISO */ + _PAD_CFG_STRUCT(GPIO_93, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + /* GPIO_93: FLASH_SPI_IO2 */ + _PAD_CFG_STRUCT(GPIO_94, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + /* GPIO_95: FLASH_SPI_IO3 */ + _PAD_CFG_STRUCT(GPIO_95, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + /* GPIO_96: FLASH_SPI_CLK */ + _PAD_CFG_STRUCT(GPIO_96, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_DISABLE), PAD_PULL(NATIVE)), + /* GPIO_98: PMU_PLT_RST#_CPU */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_98, 1, DEEP, UP_20K, TxLASTRxE, ENPD), + /* GPIO_99: PM_PWRBTN# */ + _PAD_CFG_STRUCT(GPIO_99, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_100: SLP_S0# */ + _PAD_CFG_STRUCT(GPIO_100, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_101: SLP_S3# */ + _PAD_CFG_STRUCT(GPIO_101, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_102: SLP_S4# */ + _PAD_CFG_STRUCT(GPIO_102, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_103: SUSPWRDNACK */ + _PAD_CFG_STRUCT(GPIO_103, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_104: Not Connected */ + PAD_NC(GPIO_104, DN_20K), + /* GPIO_105: GPIO_105 */ + PAD_NC(GPIO_105, DN_20K), + /* GPIO_106: PMU_BATLOW# */ + _PAD_CFG_STRUCT(GPIO_106, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_107: PMU_RSTBTN# */ + _PAD_CFG_STRUCT(GPIO_107, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_108: SUS_CLK */ + _PAD_CFG_STRUCT(GPIO_108, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_109: PMU_SUS_STAT# */ + _PAD_CFG_STRUCT(GPIO_109, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(IGNORE)), + /* GPIO_110: Not Connected */ + PAD_NC(GPIO_110, DN_20K), + /* GPIO_111: Not Connected */ + PAD_NC(GPIO_111, DN_20K), + /* GPIO_112: Not Connected */ + PAD_NC(GPIO_112, DN_20K), + /* GPIO_113: Not Connected */ + PAD_NC(GPIO_113, DN_20K), + /* GPIO_114: I2C_SDA_CPU */ + _PAD_CFG_STRUCT(GPIO_114, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_115: I2C_SDL_CPU */ + _PAD_CFG_STRUCT(GPIO_115, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_1K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_166: WLAN_PCIE_WAKE# */ + _PAD_CFG_STRUCT(GPIO_116, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)), + /* GPIO_117: Not Connected */ + PAD_NC(GPIO_117, DN_20K), + /* GPIO_118: Not Connected */ + PAD_NC(GPIO_118, DN_20K), + /* GPIO_119: Not Connected */ + PAD_NC(GPIO_119, DN_20K), + /* GPIO_121: WLAN_CLK_REQ# */ + _PAD_CFG_STRUCT(GPIO_120, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_121: Not Connected */ + PAD_NC(GPIO_121, DN_20K), + /* GPIO_122: Not Connected */ + PAD_NC(GPIO_122, DN_20K), + /* GPIO_123: Not Connected */ + PAD_NC(GPIO_123, DN_20K), + /* GPIO_124: DDI0_DDC_SDA */ + _PAD_CFG_STRUCT(GPIO_124, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPU)), + /* GPIO_125: DDI0_DDC_SCL */ + _PAD_CFG_STRUCT(GPIO_125, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(ENPU)), + /* GPIO_126: Not Connected */ + PAD_NC(GPIO_126, DN_20K), + /* GPIO_127: Not Connected */ + PAD_NC(GPIO_127, DN_20K), + /* GPIO_128: EDP_VDD_EN */ + _PAD_CFG_STRUCT(GPIO_128, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)), + /* GPIO_129: EDP_BKLT_EN */ + _PAD_CFG_STRUCT(GPIO_129, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)), + /* GPIO_130: eDP_BKLCTL_3P3 */ + _PAD_CFG_STRUCT(GPIO_130, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_IOSTERM(ENPD)), + /* GPIO_131: HDMI_HPD_CPU */ + _PAD_CFG_STRUCT(GPIO_131, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)), + /* GPIO_132: DDI1_HPD_SOC_N */ + _PAD_CFG_STRUCT(GPIO_132, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)), + /* GPIO_133: EDP_HPD_CPU */ + _PAD_CFG_STRUCT(GPIO_133, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPU)), + /* GPIO_134: Touch_Panel_RST# */ + PAD_NC(GPIO_134, DN_20K), + /* GPIO_135: TCH_HOME_KEY */ + PAD_NC(GPIO_135, DN_20K), + /* GPIO_136: Not Connected */ + PAD_NC(GPIO_136, DN_20K), + /* GPIO_137: Not Connected */ + PAD_NC(GPIO_137, DN_20K), + /* GPIO_138: Not Connected */ + PAD_NC(GPIO_138, DN_20K), + /* GPIO_139: Not Connected */ + PAD_NC(GPIO_139, DN_20K), + /* GPIO_140: Not Connected */ + PAD_NC(GPIO_140, DN_20K), + /* GPIO_141: Not Connected */ + PAD_NC(GPIO_141, DN_20K), + /* GPIO_142: PMU_WAKE# */ + _PAD_CFG_STRUCT(GPIO_142, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | + (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPU)), + /* GPIO_143: Not Connected */ + PAD_NC(GPIO_143, DN_20K), + /* GPIO_144: Not Connected */ + PAD_NC(GPIO_144, DN_20K), + /* GPIO_145: Not Connected */ + PAD_NC(GPIO_145, DN_20K), + /* GPIO_146: Not Connected */ + PAD_NC(GPIO_146, DN_20K), + /* GPIO_147: LPC_SERIRQ */ + _PAD_CFG_STRUCT(GPIO_147, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSTERM(ENPU)), + /* GPIO_148: LPC_CLK0 */ + _PAD_CFG_STRUCT(GPIO_148, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(HIZCRx1)), + /* GPIO_149: LPC_CLK_DBG_CPU */ + _PAD_CFG_STRUCT(GPIO_149, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(HIZCRx1)), + /* GPIO_150: LPC_AD0 */ + _PAD_CFG_STRUCT(GPIO_150, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPU)), + /* GPIO_151: LPC_AD1 */ + _PAD_CFG_STRUCT(GPIO_151, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPU)), + /* GPIO_152: LPC_AD2 */ + _PAD_CFG_STRUCT(GPIO_152, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPU)), + /* GPIO_153: LPC_AD3 */ + _PAD_CFG_STRUCT(GPIO_153, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPU)), + /* GPIO_154: LPC_CLKRUN# */ + _PAD_CFG_STRUCT(GPIO_154, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + /* GPIO_155: LPC_FRAME# */ + _PAD_CFG_STRUCT(GPIO_155, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | + PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPU)), + + /* ----- GPIO Group Audio ----- */ + /* GPIO_156: FP_INT# */ + PAD_NC(GPIO_156, DN_20K), + /* GPIO_157: Not Connected */ + PAD_NC(GPIO_157, DN_20K), + /* GPIO_158: Not Connected */ + PAD_NC(GPIO_158, DN_20K), + /* GPIO_159: Not Connected */ + PAD_NC(GPIO_159, DN_20K), + /* GPIO_160: Not Connected */ + PAD_NC(GPIO_160, DN_20K), + /* GPIO_161: GPIO_161 */ + PAD_CFG_GPI_TRIG_OWN(GPIO_161, DN_20K, DEEP, OFF, ACPI), + /* GPIO_162: Not Connected */ + PAD_NC(GPIO_162, DN_20K), + /* GPIO_163: GPIO_163 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_163, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_164: GPIO_164 */ + PAD_CFG_GPI_TRIG_OWN(GPIO_164, DN_20K, DEEP, OFF, ACPI), + /* GPIO_165: GPIO_165 */ + PAD_NC(GPIO_165, DN_20K), + /* GPIO_166: HDA_BCLK_CPU_R */ + _PAD_CFG_STRUCT(GPIO_166, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPD)), + /* GPIO_167: HDA_SYNC_CPU_R */ + _PAD_CFG_STRUCT(GPIO_167, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPD)), + /* GPIO_168: GPIO_168 */ + _PAD_CFG_STRUCT(GPIO_168, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1)), + /* GPIO_169: HDA_SDATAOUT */ + _PAD_CFG_STRUCT(GPIO_169, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPD)), + /* GPIO_170: HDA_RST# */ + _PAD_CFG_STRUCT(GPIO_170, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | + PAD_IOSTERM(ENPD)), + /* GPIO_171: Not Connected */ + PAD_NC(GPIO_171, DN_20K), + /* GPIO_172: Not Connected */ + PAD_NC(GPIO_172, DN_20K), + /* GPIO_173: Not Connected */ + PAD_NC(GPIO_173, DN_20K), + /* GPIO_174: GPIO_174 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_174, 1, DEEP, DN_20K, TxLASTRxE, ENPU), + /* GPIO_175: GPIO_175 */ + PAD_CFG_GPI_TRIG_OWN(GPIO_175, DN_20K, DEEP, OFF, ACPI), + + /* ----- GPIO Group SCC ----- */ + /* GPIO_176: Not Connected */ + PAD_NC(GPIO_176, DN_20K), + /* GPIO_177: TP_INT# */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_177, NONE, PLTRST), + /* GPIO_178: Not Connected */ + PAD_NC(GPIO_178, DN_20K), + /* GPIO_187: Not Connected */ + PAD_NC(GPIO_187, DN_20K), + /* GPIO_179: Not Connected */ + PAD_NC(GPIO_179, DN_20K), + /* GPIO_181: Not Connected */ + PAD_NC(GPIO_181, DN_20K), + /* GPIO_182: Not Connected */ + PAD_NC(GPIO_182, DN_20K), + /* GPIO_183: Not Connected */ + PAD_NC(GPIO_183, DN_20K), + /* GPIO_184: Not Connected */ + PAD_NC(GPIO_184, DN_20K), + /* GPIO_187: WLAN_RST_N_R */ + _PAD_CFG_STRUCT(GPIO_185, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | + PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + /* GPIO_186: Not Connected */ + PAD_NC(GPIO_186, DN_20K), + /* GPIO_188: Not Connected */ + PAD_NC(GPIO_188, DN_20K), + /* GPIO_210: Not Connected */ + PAD_NC(GPIO_210, DN_20K), + /* GPIO_189: Not Connected */ + PAD_NC(GPIO_189, DN_20K), + /* GPIO_190: Not Connected */ + PAD_NC(GPIO_190, DN_20K), + /* GPIO_191: GPIO_191 */ + _PAD_CFG_STRUCT(GPIO_191, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + /* GPIO_192: CNVI_BRI_RSP */ + _PAD_CFG_STRUCT(GPIO_192, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | + PAD_IOSTERM(ENPU)), + /* GPIO_192: CNVI_RGI_DT */ + _PAD_CFG_STRUCT(GPIO_193, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + /* GPIO_192: GPIO_194 */ + _PAD_CFG_STRUCT(GPIO_194, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | + PAD_IOSTERM(ENPU)), + /* GPIO_192: CNVI_RF_RESET_N */ + _PAD_CFG_STRUCT(GPIO_195, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + /* GPIO_196: GPIO_196 */ + _PAD_CFG_STRUCT(GPIO_196, PAD_FUNC(NF1) | PAD_RESET(DEEP) | + PAD_TRIG(OFF), PAD_IOSSTATE(IGNORE)), + /* GPIO_198: EMMC_CLK */ + PAD_NC(GPIO_198, DN_20K), + /* GPIO_200: EMMC_DATA_0 */ + PAD_NC(GPIO_200, DN_20K), + /* GPIO_201: EMMC_DATA_1 */ + PAD_NC(GPIO_201, DN_20K), + /* GPIO_202: EMMC_DATA_2 */ + PAD_NC(GPIO_202, DN_20K), + /* GPIO_203: EMMC_DATA_3 */ + PAD_NC(GPIO_203, DN_20K), + /* GPIO_204: EMMC_DATA_4 */ + PAD_NC(GPIO_204, DN_20K), + /* GPIO_205: EMMC_DATA_5 */ + PAD_NC(GPIO_205, DN_20K), + /* GPIO_206: EMMC_DATA_6 */ + PAD_NC(GPIO_206, DN_20K), + /* GPIO_207: EMMC_DATA_7 */ + PAD_NC(GPIO_207, DN_20K), + /* GPIO_208: EMMC_CMD */ + PAD_NC(GPIO_208, DN_20K), + /* GPIO_209: EMMC_STROBE */ + PAD_NC(GPIO_209, DN_20K), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/lite/variants/glkr/romstage.c b/src/mainboard/starlabs/lite/variants/glkr/romstage.c new file mode 100644 index 0000000..9483ec6 --- /dev/null +++ b/src/mainboard/starlabs/lite/variants/glkr/romstage.c @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <string.h> + +static const struct lpddr4_sku skus[] = { + [0] = { + .speed = LP4_SPEED_2133, + .ch0_rank_density = LP4_8Gb_DENSITY, + .ch1_rank_density = LP4_8Gb_DENSITY, + .ch0_dual_rank = 1, + .ch1_dual_rank = 1, + .part_num = "D9SKJ", + }, +}; + +static const struct lpddr4_cfg lp4cfg = { + .skus = skus, + .num_skus = ARRAY_SIZE(skus), +}; + +static const uint8_t ch0_bit_swizzling[] = { + 0x0f, 0x0b, 0x0d, 0x0e, 0x09, 0x0c, 0x0a, 0x08, + 0x06, 0x04, 0x05, 0x07, 0x03, 0x02, 0x01, 0x00, + 0x1e, 0x19, 0x18, 0x1c, 0x1d, 0x1b, 0x1f, 0x1a, + 0x14, 0x15, 0x17, 0x10, 0x16, 0x12, 0x11, 0x13 +}; + +static const uint8_t ch1_bit_swizzling[] = { + 0x03, 0x05, 0x06, 0x07, 0x01, 0x04, 0x02, 0x00, + 0x0c, 0x0d, 0x0e, 0x0b, 0x0a, 0x08, 0x09, 0x0f, + 0x10, 0x16, 0x15, 0x13, 0x14, 0x17, 0x12, 0x11, + 0x1f, 0x1e, 0x1b, 0x19, 0x18, 0x1d, 0x1c, 0x1a +}; + +static const uint8_t ch2_bit_swizzling[] = { + 0x08, 0x0d, 0x0b, 0x0e, 0x09, 0x0f, 0x0c, 0x0a, + 0x04, 0x00, 0x02, 0x06, 0x05, 0x07, 0x03, 0x01, + 0x1b, 0x1c, 0x1f, 0x1d, 0x1a, 0x18, 0x19, 0x1e, + 0x17, 0x12, 0x15, 0x16, 0x13, 0x10, 0x14, 0x11 +}; + +static const uint8_t ch3_bit_swizzling[] = { + 0x03, 0x07, 0x06, 0x05, 0x01, 0x04, 0x02, 0x00, + 0x0c, 0x0f, 0x0d, 0x0e, 0x0a, 0x08, 0x09, 0x0b, + 0x10, 0x11, 0x12, 0x13, 0x16, 0x14, 0x17, 0x15, + 0x1c, 0x1e, 0x1d, 0x19, 0x1f, 0x18, 0x1b, 0x1a +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *config = &memupd->FspmConfig; + + config->Package = 0x01, + config->Profile = 0x06, + config->MemoryDown = 0x01, + config->DDR3LPageSize = 0x01, + config->DDR3LASR = 0x00, + config->ScramblerSupport = 0x01, + config->ChannelHashMask = 0x36, + config->SliceHashMask = 0x09, + config->InterleavedMode = 0x02, + config->ChannelsSlicesEnable = 0x00, + config->MinRefRate2xEnable = 0x00, + config->DualRankSupportEnable = 0x01, + config->RmtMode = 0x00, + config->MemorySizeLimit = 0x00, + config->LowMemoryMaxValue = 0x00, + config->DisableFastBoot = 0x00, + config->HighMemoryMaxValue = 0x00, + config->DIMM0SPDAddress = 0x00, + config->DIMM1SPDAddress = 0x00, + + config->Ch0_RankEnable = 0x03, + config->Ch0_DeviceWidth = 0x01, + config->Ch0_DramDensity = 0x02, + config->Ch0_Option = 0x03, + config->Ch0_OdtConfig = 0x02, + config->Ch0_TristateClk1 = 0x00, + config->Ch0_Mode2N = 0x00, + config->Ch0_OdtLevels = 0x00, + + config->Ch1_RankEnable = 0x03, + config->Ch1_DeviceWidth = 0x01, + config->Ch1_DramDensity = 0x02, + config->Ch1_Option = 0x03, + config->Ch1_OdtConfig = 0x02, + config->Ch1_TristateClk1 = 0x00, + config->Ch1_Mode2N = 0x00, + config->Ch1_OdtLevels = 0x00, + + config->Ch2_RankEnable = 0x03, + config->Ch2_DeviceWidth = 0x01, + config->Ch2_DramDensity = 0x02, + config->Ch2_Option = 0x03, + config->Ch2_OdtConfig = 0x00, + config->Ch2_TristateClk1 = 0x00, + config->Ch2_Mode2N = 0x00, + config->Ch2_OdtLevels = 0x00, + + config->Ch3_RankEnable = 0x03, + config->Ch3_DeviceWidth = 0x01, + config->Ch3_DramDensity = 0x02, + config->Ch3_Option = 0x03, + config->Ch3_OdtConfig = 0x00, + config->Ch3_TristateClk1 = 0x00, + config->Ch3_Mode2N = 0x00, + config->Ch3_OdtLevels = 0x00, + + config->RmtCheckRun = 0x00, + config->RmtMarginCheckScaleHighThreshold = 0x00; + config->MsgLevelMask = 0x00; + + memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling, + sizeof(ch0_bit_swizzling)); + memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling, + sizeof(ch1_bit_swizzling)); + memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling, + sizeof(ch2_bit_swizzling)); + memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling, + sizeof(ch3_bit_swizzling)); +} + +void mainboard_save_dimm_info(void) +{ + save_lpddr4_dimm_info(&lp4cfg, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1cf2846a139004e9bec7bb27e9afe07b7e6f64f Gerrit-Change-Number: 62706 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: ec/starlabs/merlin: Add GLKR variant
by Sean Rhodes (Code Review) 09 Mar '22

09 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62705 ) Change subject: ec/starlabs/merlin: Add GLKR variant ...................................................................... ec/starlabs/merlin: Add GLKR variant Add GLKR (N5030) Lite Mk IV variant Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 --- A src/ec/starlabs/merlin/variants/glkr/ecdefs.h A src/ec/starlabs/merlin/variants/glkr/emem.asl A src/ec/starlabs/merlin/variants/glkr/events.asl 3 files changed, 280 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62705/1 diff --git a/src/ec/starlabs/merlin/variants/glkr/ecdefs.h b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h new file mode 100644 index 0000000..defb879 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/ecdefs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <stdint.h> + +/* + * EC communication interface for Nuvoton Embedded Controller. + */ + +#ifndef _EC_STARLABS_GLK_EC_DEFS_H +#define _EC_STARLABS_GLK_EC_DEFS_H + +/* Nuvoton chip ID byte values. */ +#define Nuvoton_CHIPID_VAL 0x0985 + +/* EC RAM offsets. */ +#define ECRAM_TRACKPAD_STATE 0x14 +#define ECRAM_KBL_STATE 0x16 +#define ECRAM_KBL_BRIGHTNESS 0x17 +#define ECRAM_KBL_TIMEOUT 0x12 +#define ECRAM_FN_LOCK_STATE 0x15 +#define ECRAM_FN_CTRL_REVERSE 0x13 +#define ECRAM_MAX_CHARGE dead_code_t(uint8_t) +#define ECRAM_FAN_MODE dead_code_t(uint8_t) + +#endif diff --git a/src/ec/starlabs/merlin/variants/glkr/emem.asl b/src/ec/starlabs/merlin/variants/glkr/emem.asl new file mode 100644 index 0000000..df30693 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/emem.asl @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ECF2, EmbeddedControl, 0x00, 0x100) +Field (ECF2, ByteAcc, Lock, Preserve) +{ + Offset(0x00), + ECMV, 8, // Major Version Number + ECSV, 8, // Minor Version Number + KBVS, 8, // Keyboard Controller Version + ECTV, 8, // Test Version Number + + Offset(0x11), + TPLE, 8, // Trackpad State + AFG3, 8, // After G3 + CLTP, 8, // Close Trackpad + WKOL, 8, // Wake on Lid + KLSE, 8, // Keyboard Backlight State + KLBE, 8, // Keyboard Backlight Brightness + + Offset(0x1a), + KLTE, 8, // Keyboard Backlight Timeout + + Offset(0x22), + ECT0, 8, // EC Build Time 0 + ECT1, 8, // EC Build Time 1 + ECT2, 8, // EC Build Time 2 + ECT3, 8, // EC Build Time 3 + ECT4, 8, // EC Build Time 4 + ECT5, 8, // EC Build Time 5 + ECT6, 8, // EC Build Time 6 + ECT7, 8, // EC Build Time 7 + ECT8, 8, // EC Build Time 8 + ECT9, 8, // EC Build Time 9 + + Offset(0x2c), + FLKE, 8, // Function Lock State + + Offset(0x30), + STEF, 8, // Sensor T Error F + ECD0, 8, // EC Build Date 0 + ECD1, 8, // EC Build Date 1 + ECD2, 8, // EC Build Date 2 + ECD3, 8, // EC Build Date 3 + ECD4, 8, // EC Build Date 4 + ECD5, 8, // EC Build Date 5 + ECD6, 8, // EC Build Date 6 + ECD7, 8, // EC Build Date 7 + ECD8, 8, // EC Build Date 8 + ECD9, 8, // EC Build Date 9 + + Offset(0x40), + SHIP, 8, // Shipping Mode Flag + LEDF, 8, // LED Control Flag + LIDF, 8, // Lid Flag + KBFL, 8, // Keyboard Flag + CYCC, 8, // Cycle Count + + Offset(0x46), + BFCP, 8, // Battery Full Charge Percentage + + Offset(0x62), + TSE2, 8, // Sensor 2 Temperature + SENF, 8, // Sensor F + TSHT, 8, // Thermal Sensor High Trip Point + TSLT, 8, // Thermal Sensor Low Trip Point + THER, 8, // Thermal Source + + Offset(0x70), + CPUT, 8, // PECI CPU Temperature + PMXT, 8, // PLMX Temperature + CHAR, 8, // Charger Temperature + + Offset(0x7e), + OCTF, 8, // OEM Control Flag + LSTE, 1, // Lid Status + , 7, // Reserved + + Offset(0x80), + ECPS, 8, // AC & Battery status + B1MN, 8, // Battery Model Number Code + B1SN, 16, // Battery Serial Number + B1DC, 16, // Battery Design Capacity + B1DV, 16, // Battery Design Voltage + B1FC, 16, // Battery Last Full Charge Capacity + B1TP, 16, // Battery Trip Point + B1ST, 8, // Battery State + B1PR, 16, // Battery Present Rate + B1RC, 16, // Battery Remaining Capacity + B1PV, 16, // Battery Present Voltage + BPRP, 8, // Battery Remaining percentage + BT1A, 8, // Bt1 ASOC + BT1T, 16, // Bt1 Temperature + BT1C, 8, // Bt1 Control + + // Unicorn - doesn't actually exist + Offset(0x9d), + OPWE, 8, // OPM write to EC flag for UCSI + // Unicorn - doesn't actually exist + + Offset(0xbf), + EJ8A, 8, // EJ898A Firmware Version + + Offset(0xc0), + MGI0, 8, // UCSI DS MGI 0 + MGI1, 8, // UCSI DS MGI 1 + MGI2, 8, // UCSI DS MGI 2 + MGI3, 8, // UCSI DS MGI 3 + MGI4, 8, // UCSI DS MGI 4 + MGI5, 8, // UCSI DS MGI 5 + MGI6, 8, // UCSI DS MGI 6 + MGI7, 8, // UCSI DS MGI 7 + MGI8, 8, // UCSI DS MGI 8 + MGI9, 8, // UCSI DS MGI 9 + MGIA, 8, // UCSI DS MGI A + MGIB, 8, // UCSI DS MGI B + MGIC, 8, // UCSI DS MGI C + MGID, 8, // UCSI DS MGI D + MGIE, 8, // UCSI DS MGI E + MGIF, 8, // UCSI DS MGI F + + Offset(0xd0), + MGO0, 8, // UCSI DS MGO 0 + MGO1, 8, // UCSI DS MGO 1 + MGO2, 8, // UCSI DS MGO 2 + MGO3, 8, // UCSI DS MGO 3 + MGO4, 8, // UCSI DS MGO 4 + MGO5, 8, // UCSI DS MGO 5 + MGO6, 8, // UCSI DS MGO 6 + MGO7, 8, // UCSI DS MGO 7 + MGO8, 8, // UCSI DS MGO 8 + MGO9, 8, // UCSI DS MGO 9 + MGOA, 8, // UCSI DS MGO A + MGOB, 8, // UCSI DS MGO B + MGOC, 8, // UCSI DS MGO C + MGOD, 8, // UCSI DS MGO D + MGOE, 8, // UCSI DS MGO E + MGOF, 8, // UCSI DS MGO F + + Offset(0xe0), + UCSV, 16, // UCSI DS Version + UCSD, 16, // UCSI DS Reserved + CCI0, 8, // UCSI DS CCI 0 + CCI1, 8, // UCSI DS CCI 1 + CCI2, 8, // UCSI DS CCI 2 + CCI3, 8, // UCSI DS CCI 3 + CTL0, 8, // UCSI DS Control 0 + CTL1, 8, // UCSI DS Control 0 + CTL2, 8, // UCSI DS Control 0 + CTL3, 8, // UCSI DS Control 0 + CTL4, 8, // UCSI DS Control 0 + CTL5, 8, // UCSI DS Control 0 + CTL6, 8, // UCSI DS Control 0 + CTL7, 8, // UCSI DS Control 0 + + Offset(0xf0), + P0SD, 8, // PD Port Status DD + P0S4, 8, // PD Port Status 4 + P0S5, 8, // PD Port Status 5 + P0SE, 8, // PD Port Status E + P0SA, 8, // PD Port Status 10 + P0SB, 8, // PD Port Status 11 + + Offset(0xfd), + STCD, 8, // Shutdown Code + EJ8R, 8, // EJ898A Need Reboot + EJ8E, 8, // EJ898A Error +} diff --git a/src/ec/starlabs/merlin/variants/glkr/events.asl b/src/ec/starlabs/merlin/variants/glkr/events.asl new file mode 100644 index 0000000..b962c90 --- /dev/null +++ b/src/ec/starlabs/merlin/variants/glkr/events.asl @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method (_Q0D, 0, NotSerialized) // Event: Lid Opened +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0C, 0, NotSerialized) // Event: Lid Closed +{ + \LIDS = LSTE + Notify (LID0, 0x80) +} + +Method (_Q0A, 0, NotSerialized) // Event: AC Power Connected +{ + Notify (BAT0, 0x81) + Notify (ADP1, 0x80) +} + +Method (_Q0B, 0, NotSerialized) // Event: AC Power Disconnected +{ + Notify (BAT0, 0x81) + Notify (BAT0, 0x80) +} + +Method (_Q09, 0, NotSerialized) // Event: Backlight Brightness Down +{ + ^^^^HIDD.HPEM (20) +} + +Method (_Q10, 0, NotSerialized) // Event: Backlight Brightness Up +{ + ^^^^HIDD.HPEM (19) +} + +Method (_Q08, 0, NotSerialized) // Event: Airplane Mode +{ + ^^^^HIDD.HPEM (8) +} + +Method (_QD5, 0, NotSerialized) // Event: 10 Second Power Button Pressed +{ + Notify (HIDD, 0xCE) +} + +Method (_QD6, 0, NotSerialized) // Event: 10 Second Power Button Released +{ + Notify (HIDD, 0xCF) +} + +// TODO: These need to be added +// Method (_QXX, 0, NotSerialized) // Event: Volume Up +// { +// Printf ("EC: VOLUME_UP") +// } + +// Method (_QXX, 0, NotSerialized) // Event: Volume Down +// { +// Printf ("EC: VOLUME_DOWN") +// } + +Method (_Q54, 0, NotSerialized) // Event: Power Button Press +{ + Printf ("EC: PWRBTN") +} + +Method (_Q02, 0, NotSerialized) // Event: Turn off Backlight +{ + Printf ("EC: Backlight off") +} + +Method (_Q79, 0, NotSerialized) // Event: USB Type-C +{ + Printf ("EC: USB Type-C") + UCEV() +) + +Method (_Q60, 0, NotSerialized) // Event: Trackpad Enable +{ + TPLC = TPLE +} + +Method (_Q61, 0, NotSerialized) // Event: Trackpad Disable +{ + TPLC = TPLE +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81 Gerrit-Change-Number: 62705 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/galtic: update Wifi SAR for convertibles(revise)
by Frank Chu (Code Review) 09 Mar '22

09 Mar '22

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62704 ) Change subject: mb/google/dedede/var/galtic: update Wifi SAR for convertibles(revise) ...................................................................... mb/google/dedede/var/galtic: update Wifi SAR for convertibles(revise) Add wifi sar for galnat/galnat360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) galnat (sku id:0x140000)* gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) galnat360 (sku id:0x2B0000)* BUG=b:222008376 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: I868a7416a002732736cabea48ce80548ea75e517 --- M src/mainboard/google/dedede/variants/galtic/variant.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62704/1 diff --git a/src/mainboard/google/dedede/variants/galtic/variant.c b/src/mainboard/google/dedede/variants/galtic/variant.c index 558cba6..1e62f0c 100644 --- a/src/mainboard/google/dedede/variants/galtic/variant.c +++ b/src/mainboard/google/dedede/variants/galtic/variant.c @@ -9,12 +9,16 @@ GALTIC_SKU_END = 0x12ffff, GALITH_SKU_START = 0x130000, GALITH_SKU_END = 0x13ffff, + GALNAT_SKU_START = 0x140000, + GALNAT_SKU_END = 0x14ffff, GALLOP_SKU_START = 0x150000, GALLOP_SKU_END = 0x15ffff, GALTIC360_SKU_START = 0x260000, GALTIC360_SKU_END = 0x26ffff, GALITH360_SKU_START = 0x270000, GALITH360_SKU_END = 0x27ffff, + GALNAT360_SKU_START = 0x2B0000, + GALNAT360_SKU_END = 0x2Bffff, }; const char *get_wifi_sar_cbfs_filename(void) { @@ -22,10 +26,14 @@ if (sku_id >= GALTIC_SKU_START && sku_id <= GALTIC_SKU_END) return "wifi_sar-galtic.hex"; + if (sku_id >= GALNAT_SKU_START && sku_id <= GALNAT_SKU_END) + return "wifi_sar-galnat.hex"; if (sku_id >= GALTIC360_SKU_START && sku_id <= GALTIC360_SKU_END) return "wifi_sar-galtic360.hex"; if (sku_id >= GALITH360_SKU_START && sku_id <= GALITH360_SKU_END) return "wifi_sar-galith360.hex"; + if (sku_id >= GALNAT360_SKU_START && sku_id <= GALNAT360_SKU_END) + return "wifi_sar-galnat360.hex"; return WIFI_SAR_CBFS_DEFAULT_FILENAME; } -- To view, visit https://review.coreboot.org/c/coreboot/+/62704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868a7416a002732736cabea48ce80548ea75e517 Gerrit-Change-Number: 62704 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
by Casper Chang (Code Review) 09 Mar '22

09 Mar '22

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62703 ) Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage ...................................................................... mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage Program BayHub eMMC enable pin in ram stage to prevent baseboad override the setting leads RTD3 not able to control when enter and exit suspend state. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 100 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/62703/1 diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index d4d6684..c224866 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index d2dadc3..5947b6e 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -53,6 +53,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/62703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Gerrit-Change-Number: 62703 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by Michael Niewöhner (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Tim Crawford, Michał Żygowski, Jeremy Soller, Tim Wawrzynczak, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 3: (2 comments) Patchset: PS1: > unify the Optimus support once and for all <3 File src/drivers/gfx/nvidia/optimus/optimus.c: https://review.coreboot.org/c/coreboot/+/62496/comment/7cda7d51_e636dd31 PS3, Line 195: if (config->enable_gpio.pin_count) { > to be as close to vendor ACPI as possible Just a side note: in most cases it's not the best idea to `be as close to vendor ACPI as possible`. The coreboot approach is to do it right :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 08:45:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Jeremy Soller <jeremy(a)system76.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: {drivers/security}: Replace `cb_err_t` with `enum cb_err`
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62676 ) Change subject: {drivers/security}: Replace `cb_err_t` with `enum cb_err` ...................................................................... {drivers/security}: Replace `cb_err_t` with `enum cb_err` This patch replaces remaining `cb_err_t` with `enum cb_err` after commit hash 69cc557c (commonlib/bsd: Remove cb_err_t) removes majority of `cb_err_t` instances. TEST=Able to build the brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/i2c/tpm/cr50.c M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/cr50.c M src/drivers/tpm/cr50.h M src/security/tpm/tis.h 5 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Arthur Heymans: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f8548a7..ce2278b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -514,12 +514,12 @@ { } -cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) +enum cb_err tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) { return cr50_i2c_write(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; } -cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +enum cb_err tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) { return cr50_i2c_read(addr & 0xff, buffer, bytes) ? CB_ERR : CB_SUCCESS; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 53b3a25..43fd933 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -728,12 +728,12 @@ return payload_size; } -cb_err_t tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) +enum cb_err tis_vendor_write(unsigned int addr, const void *buffer, size_t bytes) { return tpm2_write_reg(addr, buffer, bytes); } -cb_err_t tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) +enum cb_err tis_vendor_read(unsigned int addr, void *buffer, size_t bytes) { return tpm2_read_reg(addr, buffer, bytes); } diff --git a/src/drivers/tpm/cr50.c b/src/drivers/tpm/cr50.c index 4b5e813..f96e174 100644 --- a/src/drivers/tpm/cr50.c +++ b/src/drivers/tpm/cr50.c @@ -79,7 +79,7 @@ if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) return 0; - const cb_err_t ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, + const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); if (ret != CB_SUCCESS) { printk(BIOS_INFO, "Error reading from cr50\n"); @@ -92,10 +92,10 @@ /** * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. */ -cb_err_t cr50_set_board_cfg(void) +enum cb_err cr50_set_board_cfg(void) { uint32_t value; - cb_err_t ret; + enum cb_err ret; if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) return CB_ERR; @@ -139,7 +139,7 @@ return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); } -static cb_err_t cr50_parse_fw_version(const char *version_str, +static enum cb_err cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) { int epoch, major, minor; @@ -165,7 +165,7 @@ return CB_SUCCESS; } -cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version) +enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version) { if (cr50_firmware_version.epoch || cr50_firmware_version.major || cr50_firmware_version.minor) diff --git a/src/drivers/tpm/cr50.h b/src/drivers/tpm/cr50.h index 4fdd06b..f754e13 100644 --- a/src/drivers/tpm/cr50.h +++ b/src/drivers/tpm/cr50.h @@ -16,9 +16,9 @@ bool cr50_is_long_interrupt_pulse_enabled(void); /* Get the Cr50 firmware version information. */ -cb_err_t cr50_get_firmware_version(struct cr50_firmware_version *version); +enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version); /* Set the BOARD_CFG register depending on Cr50 Kconfigs */ -cb_err_t cr50_set_board_cfg(void); +enum cb_err cr50_set_board_cfg(void); #endif /* __DRIVERS_TPM_CR50_H__ */ diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index 0ef5a8a..660ec81 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -96,7 +96,7 @@ * * Returns CB_SUCCESS 0 on success, CB_ERR on failure. */ -cb_err_t tis_vendor_write(unsigned int addr, const void *sendbuf, size_t send_size); +enum cb_err tis_vendor_write(unsigned int addr, const void *sendbuf, size_t send_size); /* * tis_vendor_read() @@ -109,7 +109,7 @@ * * Returns CB_SUCCESS on success or -1 on failure. */ -cb_err_t tis_vendor_read(unsigned int addr, void *recvbuf, size_t recv_size); +enum cb_err tis_vendor_read(unsigned int addr, void *recvbuf, size_t recv_size); static inline bool tpm_first_access_this_boot(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Gerrit-Change-Number: 62676 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: {drivers/security}: Replace `cb_err_t` with `enum cb_err`
by Subrata Banik (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Patrick Georgi, Tim Wawrzynczak, Christian Walter, Angel Pons, Julius Werner, Nick Vaccaro, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62676 ) Change subject: {drivers/security}: Replace `cb_err_t` with `enum cb_err` ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: submitting now to fix the jenkin build issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/62676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3392f9c2cfb4a889a999c8ea25066c89979f0900 Gerrit-Change-Number: 62676 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 08:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022