coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Anil Kumar K, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62192 ) Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62192/comment/bf1c226f_bd3f0fb1 PS9, Line 142: cse_send_end_of_post_message > Ack Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 11:00:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Retry MEI CSE DISABLE command
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62560 ) Change subject: soc/intel/common: Retry MEI CSE DISABLE command ...................................................................... Patch Set 4: (3 comments) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/62560/comment/3fb826d5_2b3fe523 PS3, Line 14: MAX_RETRY_EOP_MSG > Hmm :) I don't think this will be required! Done https://review.coreboot.org/c/coreboot/+/62560/comment/2db5efa9_97e4d631 PS3, Line 31: decode_heci_send_receive_error > Since EOP command handler returns cse_eop_result type enum values while CSE DISABLE command handler […] Done https://review.coreboot.org/c/coreboot/+/62560/comment/10802713_f448d408 PS3, Line 77: cse_send_bus_disable_message > See above reason. Both handlers use own enum values, so APIs return different enum type values. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Gerrit-Change-Number: 62560 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 11:00:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Use generic enum type values
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Patrick Rudolph. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62708 ) Change subject: soc/intel/common: Use generic enum type values ...................................................................... soc/intel/common: Use generic enum type values The patch uses generic enum type values for EOP command handler. So, it renames cse_eop_result enum type to cse_cmd_result and also renames the enum values to have generic name. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/62708/1 diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 87da5fc..bc6d837 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -11,11 +11,11 @@ #include <timestamp.h> #include <types.h> -enum cse_eop_result { - CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED, - CSE_EOP_RESULT_SUCCESS, - CSE_EOP_RESULT_ERROR, - CSE_EOP_RESULT_DISABLED, +enum cse_cmd_result { + CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED, + CSE_CMD_RESULT_SUCCESS, + CSE_CMD_RESULT_ERROR, + CSE_CMD_RESULT_DISABLED, }; static bool cse_disable_mei_bus(void) @@ -47,7 +47,7 @@ return true; } -static enum cse_eop_result cse_send_eop(void) +static enum cse_cmd_result cse_send_eop(void) { enum { EOP_REQUESTED_ACTION_CONTINUE = 0, @@ -74,7 +74,7 @@ cse_is_hfs1_com_soft_temp_disable()) { printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " "TEMP DISABLE state, skipping EOP\n"); - return CSE_EOP_RESULT_SUCCESS; + return CSE_CMD_RESULT_SUCCESS; } /* @@ -87,25 +87,25 @@ if (cse_is_hfs1_com_soft_temp_disable()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - return CSE_EOP_RESULT_ERROR; - return CSE_EOP_RESULT_DISABLED; + return CSE_CMD_RESULT_ERROR; + return CSE_CMD_RESULT_DISABLED; } if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); if (heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } if (resp.hdr.result) { printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } printk(BIOS_INFO, "CSE: EOP requested action: "); @@ -113,13 +113,13 @@ switch (resp.requested_actions) { case EOP_REQUESTED_ACTION_GLOBAL_RESET: printk(BIOS_INFO, "global reset\n"); - return CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED; + return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; case EOP_REQUESTED_ACTION_CONTINUE: printk(BIOS_INFO, "continue boot\n"); - return CSE_EOP_RESULT_SUCCESS; + return CSE_CMD_RESULT_SUCCESS; default: printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } } @@ -139,20 +139,20 @@ "Preventing system from booting into an insecure state.\n"); } -static void handle_cse_eop_result(enum cse_eop_result result) +static void handle_cse_eop_result(enum cse_cmd_result result) { switch (result) { - case CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED: + case CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED: printk(BIOS_INFO, "CSE requested global reset in EOP response, resetting...\n"); do_global_reset(); break; - case CSE_EOP_RESULT_SUCCESS: + case CSE_CMD_RESULT_SUCCESS: printk(BIOS_INFO, "CSE EOP successful, continuing boot\n"); break; - case CSE_EOP_RESULT_DISABLED: + case CSE_CMD_RESULT_DISABLED: printk(BIOS_INFO, "CSE is disabled, continuing boot\n"); break; - case CSE_EOP_RESULT_ERROR: /* fallthrough */ + case CSE_CMD_RESULT_ERROR: /* fallthrough */ default: printk(BIOS_ERR, "Failed to send EOP to CSE, %d\n", result); /* For vboot, trigger recovery mode if applicable, as there is -- To view, visit https://review.coreboot.org/c/coreboot/+/62708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e Gerrit-Change-Number: 62708 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Retry MEI CSE DISABLE command
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62560 to look at the new patch set (#4). Change subject: soc/intel/common: Retry MEI CSE DISABLE command ...................................................................... soc/intel/common: Retry MEI CSE DISABLE command The patch retries MEI CSE DISABLE command if cse doesn't respond or sends the garbled response. It retries the command additionally 2 more times. TEST=build and boot the Brya board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62560/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id38a172d670a0cd44643744f27b85ca7e368ccdb Gerrit-Change-Number: 62560 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Retry END_OF_POST command
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Anil Kumar K, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62192 to look at the new patch set (#10). Change subject: soc/intel/common: Retry END_OF_POST command ...................................................................... soc/intel/common: Retry END_OF_POST command The patch adds retry mechanism for EOP command. If coreboot fails to send or receive the EOP command/response, it retries the EOP command max 3 times before triggering the error handling flow. BUG=b:200251277 TEST=Verify EOP retry mechanism for brya board. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 33 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/62192/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683 Gerrit-Change-Number: 62192 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Use heci_reset() in the CSE TX and RX flows
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62587 to look at the new patch set (#3). Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows ...................................................................... soc/intel/common: Use heci_reset() in the CSE TX and RX flows The patch implements error handling as per the ME BWG guide. The BWG recommends HECI interface reset if there is timeout or malformed response is received. Also, the patch triggers HECI interface reset if cse link state is not ready in heci_send() API. TEST=Verify HECI Interface reset in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62587/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Gerrit-Change-Number: 62587 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement error codes for for heci_send_receive()
by Sridhar Siricilla (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Subrata Banik, Kane Chen, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Kane Chen, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62299 to look at the new patch set (#8). Change subject: soc/intel/common: Implement error codes for for heci_send_receive() ...................................................................... soc/intel/common: Implement error codes for for heci_send_receive() The patch implements below changes: 1. Implements different error codes and use them in appropriate failure scenarios of below functions: a. heci_send() b. recv_one_message() c. heci_receive() 2. As heci_send_receive() is updated to return appropriate error codes in different error scenarios of sending and receiving the HECI commands. As the function is updated to return 0 when success, and non-zero values in the failure scenarios, so all caller function have been updated. BUG=b:220652101 TEST=Verified CSE RX and TX APIs return error codes appropriately in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 --- M src/soc/intel/apollolake/cse.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 86 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/62299/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Gerrit-Change-Number: 62299 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62563/comment/e93f21cd_8c58df4a PS10, Line 12: meets > is met Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 10:25:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 11: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 10:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62563 to look at the new patch set (#11). Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... soc/mediatek/mt8186: Modify internal capid to 0xE0 The mainboard may not be able to disable the internal cap, so we want to set 0xe0 for all boards to minimize the internal cap. And a mainboard implementation may choose XTAL with higher cload if the frequency requirement is met, and the total capacitance can be tuned externally for different boards. BUG=b:218439447 TEST=set capid to 0xe0. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 --- M src/soc/mediatek/mt8186/rtc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62563/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 11 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022