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Change subject: libpayload/Makefile.payload: Revise config strategy
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File payloads/libpayload/Makefile.payload:
https://review.coreboot.org/c/coreboot/+/62273/comment/087d2a51_5b0d8cda
PS2, Line 125: ifneq ($(LIBPAYLOAD_DEFCONFIG),)
Please add an explanation to the commit msg
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Change subject: intel/common/block: Add APL and GLK PCI IDs for HDA
......................................................................
intel/common/block: Add APL and GLK PCI IDs for HDA
Add PCI ID's for APL/GLK so they can use HDA.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9
---
M src/soc/intel/common/block/hda/hda.c
1 file changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61804/3
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Change subject: acpi: Load logo into BGRT table
......................................................................
Abandoned
Will create new patch
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Change subject: mb/google/brya: Disable C1-state auto demotion for Brya & Brask
......................................................................
Patch Set 10:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62630/comment/08e5e6c6_9d6b3786
PS5, Line 13: disabling this feature results in 110 mW power savings
> > Hi Subrata, […]
Ack.
Hi Subrata,
I have captured the details for ADL-P as of now since it is applicable only to ADL-P SKU as of now. In case we have disabled it for other SKUs as well, shall I push patch later after verifying?
Commit Message:
https://review.coreboot.org/c/coreboot/+/62630/comment/d6a78a66_899f6ba0
PS9, Line 9: c1
> C1
Ack
https://review.coreboot.org/c/coreboot/+/62630/comment/265a1a4e_db55f9ea
PS9, Line 9: c1
> C1
Ack
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Hello Felix Singer, Anil Kumar K, build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Disable C1-state auto demotion for Brya & Brask
......................................................................
mb/google/brya: Disable C1-state auto demotion for Brya & Brask
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.
Also, disabling this feature results in 110 mW power savings during
video playback.
Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.
Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/62630/10
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Change subject: mb/lenovo/g505s/irq_tables.c: Use ALIGN_UP macro
......................................................................
mb/lenovo/g505s/irq_tables.c: Use ALIGN_UP macro
Change-Id: I2bd5e09f51918fe4c7e954edf54ab4d9bc629fd1
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/lenovo/g505s/irq_tables.c
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Hello Wisley Chen,
I'd like you to do a code review. Please visit
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Change subject: soc/intel/alderlake: Add the VccIn Aux Imon IccMax for MCHID:0x4619
......................................................................
soc/intel/alderlake: Add the VccIn Aux Imon IccMax for MCHID:0x4619
Add the VccIn Aux Imon IccMax for MCHID:0x4619
BUG=none
TEST=build
Change-Id: Id93d584c240a9b4841f110ad7c540d90f829c0da
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)
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diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index b4e833b..c905567 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -314,6 +314,7 @@
case PCI_DID_INTEL_ADL_P_ID_5:
case PCI_DID_INTEL_ADL_P_ID_6:
case PCI_DID_INTEL_ADL_P_ID_7:
+ case PCI_DID_INTEL_ADL_P_ID_10:
tdp = get_cpu_tdp();
if (tdp == TDP_45W)
return ICC_MAX_TDP_45W;
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Change subject: util/cbmem: Add FlameGraph-compatible timestamps output
......................................................................
util/cbmem: Add FlameGraph-compatible timestamps output
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.
Generating flame graph using https://github.com/brendangregg/FlameGraph:
cbmem -S > trace.txt
FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg
TEST=Run on coreboot-enabled device and extract timestamps using
-t/-T/-S options
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
---
M src/commonlib/include/commonlib/timestamp_serialized.h
M util/cbmem/cbmem.c
2 files changed, 234 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62474/7
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