coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb/google/skyrim: Add FW_CONFIG Definition
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62626 ) Change subject: mb/google/skyrim: Add FW_CONFIG Definition ...................................................................... mb/google/skyrim: Add FW_CONFIG Definition BUG=b:214415048 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 599478f..54373c4 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -1,6 +1,29 @@ # SPDX-License-Identifier: GPL-2.0-or-later fw_config - # TODO define when available + field FORM_FACTOR 0 + option FORM_FACTOR_CLAMSHELL 0 + option FORM_FACTOR_CONVERTIBLE 1 + end + field FP 1 + option FP_ABSENT 0 + option FP_PRESENT 1 + end + field WLAN 2 3 + option WLAN_MT7921LE 0 + option WLAN_RTL8852 1 + end + field WWAN 4 5 + option WWAN_DIASABLED 0 + option WWAN_FM101GL 1 + end + field IO_DB 6 7 + option IO_DB_A1_PS8811_C1_PS8818 0 + option IO_DB_A1_None_C1_ANX7483QN 1 + end + field AUDIO_DB 8 9 + option AUDIO_DB_C_ALC5682I_A_ALC1019 0 + option AUDIO_DB_C_NAU88L25YGB_A_MAX98360AENL 1 + end end chip soc/amd/sabrina 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8 Gerrit-Change-Number: 62626 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62355 ) Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI ...................................................................... cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI This change will allow the SMI handler to write to the cbmem console buffer. Normally SMIs can only be debugged using some kind of serial port (UART). By storing the SMI logs into cbmem we can debug SMIs using `cbmem -1`. Now that these logs are available to the OS we could also verify there were no errors in the SMI handler. Since SMM can write to all of DRAM, we can't trust any pointers provided by cbmem after the OS has booted. For this reason we store the cbmem console pointer as part of the SMM runtime parameters. The cbmem console is implemented as a circular buffer so it will never write outside of this area. BUG=b:221231786 TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are visible when running `cbmem -1`. Perform a suspend/resume cycle and verify new SMI events are written to the cbmem console log. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/cpu/x86/smm/smm_module_handler.c M src/cpu/x86/smm/smm_module_loader.c M src/include/console/cbmem_console.h M src/include/cpu/x86/smm.h M src/lib/Makefile.inc M src/lib/cbmem_console.c 6 files changed, 36 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index cab691d..bd4149a 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <console/cbmem_console.h> #include <console/console.h> #include <commonlib/region.h> #include <cpu/x86/smm.h> @@ -48,6 +49,12 @@ ); } +void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out) +{ + *buffer_out = smm_runtime.cbmemc; + *size_out = smm_runtime.cbmemc_size; +} + void io_trap_handler(int smif) { /* If a handler function handled a given IO trap, it diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 14e2aa3..17c6779 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -5,6 +5,7 @@ #include <stdint.h> #include <string.h> #include <rmodule.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -479,6 +480,7 @@ void *fxsave_area; size_t total_size = 0; uintptr_t base; /* The base for the permanent handler */ + const struct cbmem_entry *cbmemc; if (CONFIG(SMM_ASEG)) return smm_load_module_aseg(smram_base, smram_size, params); @@ -557,6 +559,14 @@ handler_mod_params->num_cpus = params->num_cpus; handler_mod_params->gnvs_ptr = (uintptr_t)acpi_get_gnvs(); + if (CONFIG(CONSOLE_CBMEM) && (cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE))) { + handler_mod_params->cbmemc = cbmem_entry_start(cbmemc); + handler_mod_params->cbmemc_size = cbmem_entry_size(cbmemc); + } else { + handler_mod_params->cbmemc = 0; + handler_mod_params->cbmemc_size = 0; + } + printk(BIOS_DEBUG, "%s: smram_start: 0x%lx\n", __func__, smram_base); printk(BIOS_DEBUG, "%s: smram_end: %lx\n", __func__, smram_base + smram_size); printk(BIOS_DEBUG, "%s: handler start %p\n", @@ -577,6 +587,8 @@ printk(BIOS_DEBUG, "%s: per_cpu_save_state_size = 0x%x\n", __func__, handler_mod_params->save_state_size); printk(BIOS_DEBUG, "%s: num_cpus = 0x%x\n", __func__, handler_mod_params->num_cpus); + printk(BIOS_DEBUG, "%s: cbmemc = %p, cbmemc_size = %#x\n", __func__, + handler_mod_params->cbmemc, handler_mod_params->cbmemc_size); printk(BIOS_DEBUG, "%s: total_save_state_size = 0x%x\n", __func__, (handler_mod_params->save_state_size * handler_mod_params->num_cpus)); diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 4f03a45..9a814b9 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -10,7 +10,8 @@ #define __CBMEM_CONSOLE_ENABLE__ (CONFIG(CONSOLE_CBMEM) && \ (ENV_RAMSTAGE || ENV_SEPARATE_VERSTAGE || ENV_POSTCAR || \ - ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)))) + ENV_ROMSTAGE || (ENV_BOOTBLOCK && CONFIG(BOOTBLOCK_CONSOLE)) || \ + (ENV_SMM && CONFIG(DEBUG_SMI)))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } @@ -28,3 +29,6 @@ void cbmem_dump_console_to_uart(void); void cbmem_dump_console(void); #endif + +/* Retrieves the location of the CBMEM Console buffer in SMM mode */ +void smm_get_cbmemc_buffer(void **buffer_out, size_t *size_out); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 8ea8336..28d95e1 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -61,6 +61,8 @@ u32 save_state_size; u32 num_cpus; u32 gnvs_ptr; + u32 cbmemc_size; + void *cbmemc; uintptr_t save_state_top[CONFIG_MAX_CPUS]; } __packed; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5e3ce50..f3da503 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -220,6 +220,9 @@ smm-y += fmap.c smm-y += cbfs.c memcmp.c smm-$(CONFIG_GENERIC_UDELAY) += timer.c +ifeq ($(CONFIG_DEBUG_SMI),y) +smm-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c +endif bootblock-y += version.c romstage-y += version.c diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 0c56095..783f336 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -84,6 +84,13 @@ if (ENV_ROMSTAGE_OR_BEFORE) { /* Pre-RAM environments use special buffer placed by linker script. */ init_console_ptr(_preram_cbmem_console, REGION_SIZE(preram_cbmem_console)); + } else if (ENV_SMM) { + void *cbmemc = NULL; + size_t cbmemc_size = 0; + + smm_get_cbmemc_buffer(&cbmemc, &cbmemc_size); + + init_console_ptr(cbmemc, cbmemc_size); } else { /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ init_console_ptr(static_console, sizeof(static_console)); -- To view, visit https://review.coreboot.org/c/coreboot/+/62355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79 Gerrit-Change-Number: 62355 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62632 ) Change subject: mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8 ...................................................................... mb/google/brya/var/redrix{4es}: Config VR_DOMAIN_GT's slew rate to 1/8 Config VR_DOMAIN_GT's slew rate to 1/8 as well. BUG=b:204009588 TEST=build and verified by Power team. Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index d1d9e8c..3f9c81d 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -39,7 +39,9 @@ # Acoustic settings register "AcousticNoiseMitigation" = "1" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 586c90e..0c9c174 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -39,7 +39,9 @@ # Acoustic settings register "AcousticNoiseMitigation" = "1" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" -- To view, visit https://review.coreboot.org/c/coreboot/+/62632 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2 Gerrit-Change-Number: 62632 Gerrit-PatchSet: 4 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/bry/anahera{4es}: Disable TCSS port1
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62634 ) Change subject: mb/google/bry/anahera{4es}: Disable TCSS port1 ...................................................................... mb/google/bry/anahera{4es}: Disable TCSS port1 Disable unused TCSS Port1. BUG=b:223082190 TEST=Build Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62634 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 0db917e..9934dee 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -73,6 +73,7 @@ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" device domain 0 on device ref igpu on chip drivers/gfx/generic @@ -139,6 +140,7 @@ device generic 0 on end end end + device ref tbt_pcie_rp1 off end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index 6136565..0d36ddf 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -65,6 +65,7 @@ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" device domain 0 on device ref igpu on chip drivers/gfx/generic @@ -131,6 +132,7 @@ device generic 0 on end end end + device ref tbt_pcie_rp1 off end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f4b7d89a1e37a00c58201ecc88bb336d0932c9 Gerrit-Change-Number: 62634 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigation
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62633 ) Change subject: mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigation ...................................................................... mb/google/brya/var/anahera{4es}: Configure Acoustic noise mitigation Enable Acoustic noise mitigation and set slew rate to 1/8 BUG=b:223082189 TEST=build and verified by power team Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 6a79a96..0db917e 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -23,6 +23,13 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb index ab432e9..6136565 100644 --- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb @@ -23,6 +23,13 @@ end chip soc/intel/alderlake register "SaGv" = "SaGv_Enabled" + # Acoustic settings + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/62633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083 Gerrit-Change-Number: 62633 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/nissa: Add fmd file for nissa
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62372 ) Change subject: mb/google/nissa: Add fmd file for nissa ...................................................................... mb/google/nissa: Add fmd file for nissa Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash layout for brya is of 32MB size, and nissa is expected to have 16MB SPI NOR flash. The current composition of AP firmware exceeds 16MB. To get an estimate of the unutilized region in the current flash layout for nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware size to under 16MB and to remove the RW_UNUSED regions from the final fmd file. Below table gives the size reduction from brya fmd to nissa fmd: +----------------+-------------------+---------------+ | Region | Earlier size (KB) | New size (KB) | +================+===================+===============+ | SI_ME | 5116 | 3772 | +----------------+-------------------+---------------+ | RW_SECTION_A/B | 8192 | 4344 | +----------------+-------------------+---------------+ | VBLOCK_A/B | 64 | 8 | +----------------+-------------------+---------------+ | ME_RW_A/B* | 3008 | 1434 | +----------------+-------------------+---------------+ | RW_LEGACY | 2048 | 1024 | +----------------+-------------------+---------------+ | RW_ELOG | 16 | 4 | +----------------+-------------------+---------------+ | SHARED_DATA | 8 | 4 | +----------------+-------------------+---------------+ | VBLOCK_DEV | 8 | 0 | +----------------+-------------------+---------------+ | RW_SPD_CACHE | 4 | 0 | +----------------+-------------------+---------------+ | RW_NVRAM | 24 | 8 | +----------------+-------------------+---------------+ | WP_RO | 8192 | 4096 | +----------------+-------------------+---------------+ | GBB | 448 | 12 | +----------------+-------------------+---------------+ *Based on LZMA compression on ME_RW_A/B regions. With LZMA compression, this region can be 1434K. Without this, ~665K will be more in each of these regions. Patch: https://review.coreboot.org/c/coreboot/+/62358/ BUG=b:202783191 BRANCH=None TEST=Build and boot Nivviks. Cq-Depend: chrome-internal:4584911 Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/chromeos-nissa.fmd 2 files changed, 59 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 8880006..b48124b 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -125,6 +125,7 @@ config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" config TPM_TIS_ACPI_INTERRUPT diff --git a/src/mainboard/google/brya/chromeos-nissa.fmd b/src/mainboard/google/brya/chromeos-nissa.fmd new file mode 100644 index 0000000..f6790e4 --- /dev/null +++ b/src/mainboard/google/brya/chromeos-nissa.fmd @@ -0,0 +1,58 @@ +FLASH 32M { + SI_ALL 3776K { + SI_DESC 4K + SI_ME { + CSE_LAYOUT 8K + CSE_RO 1360K + CSE_DATA 420K + # 64-KiB aligned to optimize RW erases during CSE update. + CSE_RW 1984K + } + } + SI_BIOS 28992K { + RW_SECTION_A 4344K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + ME_RW_A(CBFS) 1434K + } + RW_LEGACY(CBFS) 1M + RW_MISC 152K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 4K { + SHARED_DATA 4K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 8K + } + # RW UNUSED Region 1. + RW_UNUSED_1 7088K + # This section starts at the 16M boundary in SPI flash. + # ADL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 4344K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + ME_RW_B(CBFS) 1434K + } + # RW UNUSED Region 2. + RW_UNUSED_2 7944K + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755 Gerrit-Change-Number: 62372 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62570 ) Change subject: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig ...................................................................... mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62570 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6690a90..8880006 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -64,6 +64,7 @@ select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW select SYSTEM_TYPE_LAPTOP if BOARD_GOOGLE_BRYA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/62570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Gerrit-Change-Number: 62570 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... soc/intel/common: Add Kconfig to enable compression on ME_RW blobs Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B regions. On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B regions. FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none FMAP REGION: ME_RW_B Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 164159c..fb75486 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -150,6 +150,13 @@ help CBFS path and file name for Intel CSE sub-partition NPHY binary +config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW + bool + default n + depends on SOC_INTEL_CSE_LITE_SKU + help + Enable compression on Intel CSE CBFS RW blob + if STITCH_ME_BIN config CSE_COMPONENTS_PATH diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11a4891..472ae95 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -85,6 +85,9 @@ $(CSE_LITE_ME_RW)-file := $(CSE_RW_FILE) $(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) $(CSE_LITE_ME_RW)-type := raw +ifeq ($(CONFIG_SOC_INTEL_CSE_LITE_COMPRESS_ME_RW),y) +$(CSE_LITE_ME_RW)-compression := LZMA +endif $(obj)/cse_rw.version: @echo '$(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION))' > $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 6 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62574 ) Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... cbfstool/linux_trampoline: Fill the ACPI RSDP entry With LinuxBoot Linux relied on the legacy method of fetching the RSDP pointer to get ACPI. This uses a more modern approach available since 2018 on the Linux kernel, which involves filling in the zero page. This method takes precedence over any other method of fetching the RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are threatening that legacy code will be removed from Linux so it's best to already adapt to that possibility. Tested on Qemu: - With qemu the RSDP is always in the EBDA, so checking if Linux uses the provided pointer is better done with a forced bad entry - With a fake bad pointer Linux correctly does not find RDSP Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 2 files changed, 22 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 7268528..767c8be 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -13,7 +13,9 @@ #define CB_TAG_FORWARD 0x11 #define CB_TAG_MEMORY 0x1 #define CB_TAG_FRAMEBUFFER 0x12 +#define CB_TAG_ACPI_RSDP 0x43 +#define ACPI_RSDP_ADDR 0x70 #define E820_NR_OFFSET 0x1e8 #define LINUX_ENTRY_OFFSET 0x214 #define E820_OFFSET 0x2d0 @@ -52,7 +54,7 @@ .testMemory: cmp $CB_TAG_MEMORY, (%ebx) -jne .testFramebuffer +jne .testAcpiRsdp /* memory tag: copy e820 map and entry count. also determine alt_mem_k */ mov 4(%ebx), %eax @@ -87,6 +89,16 @@ add $20, %edi jmp .test_e820_entry +.testAcpiRsdp: +cmp $CB_TAG_ACPI_RSDP, (%ebx) +jne .testFramebuffer + +mov 8(%ebx), %eax +mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR) +mov 12(%ebx), %eax +mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR + 4) +jmp .endScan + .testFramebuffer: cmp $CB_TAG_FRAMEBUFFER, (%ebx) jne .endScan diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index b804c80..46bb800 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -3,17 +3,18 @@ unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, - 0xcb, 0x0f, 0x84, 0xaa, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, + 0xcb, 0x0f, 0x84, 0xc5, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x53, 0x8b, 0x43, 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0x89, 0xc6, 0xbf, 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, 0x00, 0x89, 0xf0, 0x91, 0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xa1, - 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x18, 0x83, 0x7f, + 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x2f, 0x83, 0x7f, 0x10, 0x0c, 0x7e, 0x07, 0xc7, 0x47, 0x10, 0x02, 0x00, 0x00, 0x00, 0x48, 0x83, 0xc7, 0x14, 0xeb, - 0xe8, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x75, 0x93, 0xb8, 0x00, 0x00, 0x04, - 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, - 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, - 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, - 0x00, 0xf4, 0xeb, 0xfd + 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x12, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, + 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0xeb, 0x05, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, + 0x49, 0x0f, 0x85, 0x78, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, + 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, + 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, + 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd }; -unsigned int trampoline_len = 212; +unsigned int trampoline_len = 239; -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: libpayload/Makefile.payload: Fix CFLAGS
by Thomas Heijligen (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Julius Werner. Thomas Heijligen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62248 ) Change subject: libpayload/Makefile.payload: Fix CFLAGS ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ec15f169d51c7a32ca86e54a98a2ce0e3b51e6d Gerrit-Change-Number: 62248 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:21:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022