coreboot-gerrit March 2022

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Change in coreboot[master]: ec/starlabs: Store the correct value for TPLE when suspending
by Angel Pons (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Sean Rhodes, Andy Pont. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62604 ) Change subject: ec/starlabs: Store the correct value for TPLE when suspending ...................................................................... Patch Set 7: (1 comment) File src/ec/starlabs/merlin/acpi/suspend.asl: https://review.coreboot.org/c/coreboot/+/62604/comment/a8133094_c8c92640 PS7, Line 8: ToInteger > Yup, it's possible for it to be 0xbb (we don't want to handle it if it is though) Hmmm, I don't follow. https://imgur.com/7vs9wC6.png -- To view, visit https://review.coreboot.org/c/coreboot/+/62604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Gerrit-Change-Number: 62604 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:51:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation: Fix broken links
by Felix Singer (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62672 ) Change subject: Documentation: Fix broken links ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File Documentation/mainboard/asus/f2a85-m.md: https://review.coreboot.org/c/coreboot/+/62672/comment/80feab25_c49de656 PS1, Line 194: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf This and many other links seem to work. -- To view, visit https://review.coreboot.org/c/coreboot/+/62672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Gerrit-Change-Number: 62672 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/trogdor: Add variant Gelarshie
by Douglas Anderson (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Paul Menzel, Bob Moragues, Julius Werner, Mars Chen. Douglas Anderson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62642 ) Change subject: mb/google/trogdor: Add variant Gelarshie ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/trogdor/Kconfig: https://review.coreboot.org/c/coreboot/+/62642/comment/276b60ee_fd69830c PS3, Line 26: default y if BOARD_GOOGLE_COACHZ If you're similar to coachz, should you set HAS_FINGERPRINT ? -- To view, visit https://review.coreboot.org/c/coreboot/+/62642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9 Gerrit-Change-Number: 62642 Gerrit-PatchSet: 3 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Store the correct value for TPLE when suspending
by Sean Rhodes (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Andy Pont, Angel Pons. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62604 ) Change subject: ec/starlabs: Store the correct value for TPLE when suspending ...................................................................... Patch Set 7: (1 comment) File src/ec/starlabs/merlin/acpi/suspend.asl: https://review.coreboot.org/c/coreboot/+/62604/comment/7cf73f15_855e0fbb PS7, Line 8: ToInteger > Is `ToInteger` needed? Yup, it's possible for it to be 0xbb (we don't want to handle it if it is though) -- To view, visit https://review.coreboot.org/c/coreboot/+/62604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Gerrit-Change-Number: 62604 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:47:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/starlabs: Store the correct value for TPLE when suspending
by Angel Pons (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Sean Rhodes, Andy Pont. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62604 ) Change subject: ec/starlabs: Store the correct value for TPLE when suspending ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/ec/starlabs/merlin/acpi/suspend.asl: https://review.coreboot.org/c/coreboot/+/62604/comment/95cfb2cb_f83e8697 PS7, Line 8: ToInteger Is `ToInteger` needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/62604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I921be8aea55b95f1ba233d2640d9bae80f8c3703 Gerrit-Change-Number: 62604 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/release: Update genrelnotes with the latest version
by Patrick Georgi (Code Review) 09 Mar '22

09 Mar '22

Attention is currently required from: Martin Roth. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62440 ) Change subject: util/release: Update genrelnotes with the latest version ...................................................................... Patch Set 2: Code-Review+1 (3 comments) Patchset: PS2: Looks reasonable in general, just some minor bits that confused me. File util/release/genrelnotes: https://review.coreboot.org/c/coreboot/+/62440/comment/2d3dbaed_94b2bc3b PS2, Line 249: * "${base}"* to have it expand? https://review.coreboot.org/c/coreboot/+/62440/comment/8269ea71_04064968 PS2, Line 349: tigerlake is this intentional? -- To view, visit https://review.coreboot.org/c/coreboot/+/62440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4 Gerrit-Change-Number: 62440 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 09 Mar 2022 14:41:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... soc/mediatek/mt8186: set pin drive strength to 8mA for NOR Set NOR pin drive to 8mA to comply with HW requirement. This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=SPI SI tests for AP to NOR pass for both kingler and krabby. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/spi.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c index d4d3684..11f8b6a 100644 --- a/src/soc/mediatek/mt8186/spi.c +++ b/src/soc/mediatek/mt8186/spi.c @@ -6,6 +6,7 @@ */ #include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <spi_flash.h> #include <soc/addressmap.h> @@ -147,6 +148,14 @@ for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) { gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select); gpio_set_mode(ptr[i].gpio, ptr[i].func); + + if (gpio_set_driving(ptr[i].gpio, GPIO_DRV_8_MA) < 0) + printk(BIOS_WARNING, + "%s: failed to set pin drive to 8 mA for %d\n", + __func__, ptr[i].gpio.id); + else + printk(BIOS_DEBUG, "%s: got pin drive: %#x\n", __func__, + gpio_get_driving(ptr[i].gpio)); } } 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 18 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... soc/mediatek/mt8186: Add GPIO driving functions Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/gpio_common.h M src/soc/mediatek/mt8186/gpio.c M src/soc/mediatek/mt8186/include/soc/gpio.h 3 files changed, 352 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 283cf94..097c2b9 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -18,10 +18,39 @@ GPIO_PULL_UP = 1, }; +/* + * GPIO DRIVING + * Special IO(I2C, HDMI...) advanced drive strength: + * GPIO_DRV_ADV_125_UA: 0.125mA + * GPIO_DRV_ADV_250_UA: 0.25mA + * GPIO_DRV_ADV_500_UA: 0.5mA + * GPIO_DRV_ADV_1_MA: 1mA + */ +enum gpio_drv_adv { + GPIO_DRV_ADV_125_UA = 0, + GPIO_DRV_ADV_250_UA = 1, + GPIO_DRV_ADV_500_UA = 2, + GPIO_DRV_ADV_1_MA = 3, +}; + +struct gpio_drv_info { + uint32_t offset; + uint8_t shift; + uint8_t width; +}; + void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); +/* Normal driving function */ +int gpio_set_driving(gpio_t gpio, uint8_t drv); +int gpio_get_driving(gpio_t gpio); + +/* Advanced driving function */ +int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv); +int gpio_get_driving_adv(gpio_t gpio); + enum gpio_irq_type { IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING, diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c index bd3ab65..c96f1ea 100644 --- a/src/soc/mediatek/mt8186/gpio.c +++ b/src/soc/mediatek/mt8186/gpio.c @@ -8,6 +8,221 @@ #include <device/mmio.h> #include <gpio.h> +static const struct gpio_drv_info gpio_driving_info[] = { + [0] = { 0x0, 27, 3, }, + [1] = { 0x0, 27, 3, }, + [2] = { 0x0, 27, 3, }, + [3] = { 0x0, 27, 3, }, + [4] = { 0x10, 0, 3, }, + [5] = { 0x10, 0, 3, }, + [6] = { 0x0, 9, 3, }, + [7] = { 0x0, 9, 3, }, + [8] = { 0x0, 9, 3, }, + [9] = { 0x0, 12, 3, }, + [10] = { 0x0, 0, 3, }, + [11] = { 0x0, 3, 3, }, + [12] = { 0x0, 6, 3, }, + [13] = { 0x0, 0, 3, }, + [14] = { 0x0, 3, 3, }, + [15] = { 0x10, 3, 3, }, + [16] = { 0x10, 3, 3, }, + [17] = { 0x0, 21, 3, }, + [18] = { 0x10, 0, 3, }, + [19] = { 0x0, 27, 3, }, + [20] = { 0x0, 24, 3, }, + [21] = { 0x0, 27, 3, }, + [22] = { 0x0, 24, 3, }, + [23] = { 0x10, 0, 3, }, + [24] = { 0x10, 9, 3, }, + [25] = { 0x10, 0, 3, }, + [26] = { 0x0, 27, 3, }, + [27] = { 0x0, 27, 3, }, + [28] = { 0x10, 0, 3, }, + [29] = { 0x10, 0, 3, }, + [30] = { 0x10, 0, 3, }, + [31] = { 0x10, 3, 3, }, + [32] = { 0x0, 6, 3, }, + [33] = { 0x0, 6, 3, }, + [34] = { 0x0, 3, 3, }, + [35] = { 0x0, 3, 3, }, + [36] = { 0x0, 9, 3, }, + [37] = { 0x0, 9, 3, }, + [38] = { 0x0, 12, 3, }, + [39] = { 0x0, 9, 3, }, + [40] = { 0x0, 15, 3, }, + [41] = { 0x0, 12, 3, }, + [42] = { 0x0, 12, 3, }, + [43] = { 0x0, 12, 3, }, + [44] = { 0x10, 6, 3, }, + [45] = { 0x10, 3, 3, }, + [46] = { 0x10, 3, 3, }, + [47] = { 0x10, 6, 3, }, + [48] = { 0x0, 15, 3, }, + [49] = { 0x0, 15, 3, }, + [50] = { 0x0, 15, 3, }, + [51] = { 0x0, 18, 3, }, + [52] = { 0x10, 3, 3, }, + [53] = { 0x10, 6, 3, }, + [54] = { 0x10, 3, 3, }, + [55] = { 0x10, 3, 3, }, + [56] = { 0x10, 3, 3, }, + [57] = { 0x10, 6, 3, }, + [58] = { 0x10, 6, 3, }, + [59] = { 0x10, 3, 3, }, + [60] = { 0x0, 24, 3, }, + [61] = { 0x0, 24, 3, }, + [62] = { 0x0, 24, 3, }, + [63] = { 0x0, 24, 3, }, + [64] = { 0x0, 27, 3, }, + [65] = { 0x0, 27, 3, }, + [66] = { 0x0, 27, 3, }, + [67] = { 0x10, 0, 3, }, + [68] = { 0x0, 0, 3, }, + [69] = { 0x0, 3, 3, }, + [70] = { 0x10, 3, 3, }, + [71] = { 0x0, 6, 3, }, + [72] = { 0x0, 9, 3, }, + [73] = { 0x0, 12, 3, }, + [74] = { 0x0, 15, 3, }, + [75] = { 0x0, 18, 3, }, + [76] = { 0x0, 21, 3, }, + [77] = { 0x0, 24, 3, }, + [78] = { 0x0, 27, 3, }, + [79] = { 0x0, 24, 3, }, + [80] = { 0x0, 24, 3, }, + [81] = { 0x0, 21, 3, }, + [82] = { 0x0, 21, 3, }, + [83] = { 0x10, 3, 3, }, + [84] = { 0x0, 6, 3, }, + [85] = { 0x0, 9, 3, }, + [86] = { 0x0, 12, 3, }, + [87] = { 0x0, 15, 3, }, + [88] = { 0x0, 18, 3, }, + [89] = { 0x0, 21, 3, }, + [90] = { 0x0, 27, 3, }, + [91] = { 0x10, 0, 3, }, + [92] = { 0x10, 0, 3, }, + [93] = { 0x10, 0, 3, }, + [94] = { 0x10, 0, 3, }, + [95] = { 0x10, 3, 3, }, + [96] = { 0x0, 9, 3, }, + [97] = { 0x0, 6, 3, }, + [98] = { 0x0, 3, 3, }, + [99] = { 0x0, 18, 3, }, + [100] = { 0x0, 18, 3, }, + [101] = { 0x0, 21, 3, }, + [102] = { 0x0, 21, 3, }, + [103] = { 0x0, 21, 3, }, + [104] = { 0x0, 21, 3, }, + [105] = { 0x0, 24, 3, }, + [106] = { 0x0, 24, 3, }, + [107] = { 0x0, 24, 3, }, + [108] = { 0x0, 24, 3, }, + [109] = { 0x0, 27, 3, }, + [110] = { 0x0, 27, 3, }, + [111] = { 0x0, 27, 3, }, + [112] = { 0x0, 27, 3, }, + [113] = { 0x10, 0, 3, }, + [114] = { 0x10, 0, 3, }, + [115] = { 0x10, 6, 3, }, + [116] = { 0x10, 9, 3, }, + [117] = { 0x10, 6, 3, }, + [118] = { 0x10, 6, 3, }, + [119] = { 0x0, 18, 3, }, + [120] = { 0x0, 9, 3, }, + [121] = { 0x0, 12, 3, }, + [122] = { 0x0, 15, 3, }, + [123] = { 0x0, 21, 3, }, + [124] = { 0x0, 0, 3, }, + [125] = { 0x0, 3, 3, }, + [126] = { 0x0, 6, 3, }, + [127] = { 0x10, 12, 3, }, + [128] = { 0x10, 18, 3, }, + [129] = { 0x10, 12, 3, }, + [130] = { 0x10, 18, 3, }, + [131] = { 0x10, 15, 3, }, + [132] = { 0x10, 21, 3, }, + [133] = { 0x10, 15, 3, }, + [134] = { 0x10, 21, 3, }, + [135] = { 0x10, 6, 3, }, + [136] = { 0x10, 15, 3, }, + [137] = { 0x10, 18, 3, }, + [138] = { 0x10, 24, 3, }, + [139] = { 0x0, 21, 3, }, + [140] = { 0x0, 24, 3, }, + [141] = { 0x10, 15, 3, }, + [142] = { 0x10, 21, 3, }, + [143] = { 0x10, 9, 3, }, + [144] = { 0x10, 18, 3, }, + [145] = { 0x10, 12, 3, }, + [146] = { 0x10, 21, 3, }, + [147] = { 0x0, 12, 3, }, + [148] = { 0x0, 12, 3, }, + [149] = { 0x0, 12, 3, }, + [150] = { 0x0, 15, 3, }, + [151] = { 0x0, 15, 3, }, + [152] = { 0x0, 9, 3, }, + [153] = { 0x0, 15, 3, }, + [154] = { 0x0, 15, 3, }, + [155] = { 0x0, 18, 3, }, + [156] = { 0x0, 18, 3, }, + [157] = { 0x0, 0, 3, }, + [158] = { 0x0, 0, 3, }, + [159] = { 0x0, 0, 3, }, + [160] = { 0x0, 0, 3, }, + [161] = { 0x0, 6, 3, }, + [162] = { 0x0, 3, 3, }, + [163] = { 0x10, 12, 3, }, + /* 164 is unimplemented */ + [165] = { 0x10, 6, 3, }, + [166] = { 0x10, 6, 3, }, + [167] = { 0x10, 9, 3, }, + [168] = { 0x10, 6, 3, }, + [169] = { 0x10, 12, 3, }, + [170] = { 0x10, 9, 3, }, + [171] = { 0x10, 9, 3, }, + [172] = { 0x10, 9, 3, }, + [173] = { 0x10, 6, 3, }, + [174] = { 0x0, 9, 3, }, + [175] = { 0x0, 12, 3, }, + [176] = { 0x0, 0, 3, }, + [177] = { 0x0, 3, 3, }, + [178] = { 0x0, 6, 3, }, + [179] = { 0x0, 15, 3, }, + [180] = { 0x0, 18, 3, }, + [181] = { 0x0, 21, 3, }, + [182] = { 0x0, 24, 3, }, + [183] = { 0x0, 27, 3, }, + [184] = { 0x10, 0, 3, }, +}; + +_Static_assert(ARRAY_SIZE(gpio_driving_info) == GPIO_NUM, + "gpio_driving_info array size not match"); + +/* Unimplemented GPIOs are intentionally omitted here with width=0 */ +static const struct gpio_drv_info gpio_driving_adv_info[GPIO_NUM] = { + [127] = { 0x30, 0, 3, }, + [128] = { 0x30, 6, 3, }, + [129] = { 0x30, 0, 3, }, + [130] = { 0x30, 6, 3, }, + [131] = { 0x30, 3, 3, }, + [132] = { 0x30, 9, 3, }, + [133] = { 0x30, 0, 3, }, + [134] = { 0x30, 6, 3, }, + [135] = { 0x20, 0, 3, }, + [136] = { 0x20, 9, 3, }, + [137] = { 0x30, 3, 3, }, + [138] = { 0x30, 9, 3, }, + [139] = { 0x20, 0, 3, }, + [140] = { 0x20, 3, 3, }, + [141] = { 0x30, 3, 3, }, + [142] = { 0x30, 9, 3, }, + [143] = { 0x20, 3, 3, }, + [144] = { 0x20, 12, 3, }, + [145] = { 0x20, 6, 3, }, + [146] = { 0x20, 15, 3, }, +}; + static void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; @@ -95,3 +310,98 @@ else gpio_set_pull_pu_pd(gpio, enable, select); } + +static inline bool is_valid_drv(uint8_t drv) +{ + return drv <= GPIO_DRV_16_MA; +} + +static inline bool is_valid_drv_adv(enum gpio_drv_adv drv) +{ + return drv <= GPIO_DRV_ADV_1_MA && drv >= GPIO_DRV_ADV_125_UA; +} + +int gpio_set_driving(gpio_t gpio, uint8_t drv) +{ + uint32_t mask; + const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg, *reg_adv; + + if (!is_valid_drv(drv)) + return -1; + + reg = gpio_find_reg_addr(gpio) + info->offset; + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + + if (info->width == 0) + return -1; + + mask = BIT(info->width) - 1; + /* Check setting value is not beyond width */ + if ((uint32_t)drv > mask) + return -1; + + clrsetbits32(reg, mask << info->shift, drv << info->shift); + + /* Disable EH if supported */ + if (adv_info->width != 0) + clrbits32(reg_adv, BIT(adv_info->shift)); + + return 0; +} + +int gpio_get_driving(gpio_t gpio) +{ + const struct gpio_drv_info *info = &gpio_driving_info[gpio.id]; + void *reg; + + reg = gpio_find_reg_addr(gpio) + info->offset; + if (info->width == 0) + return -1; + + return (read32(reg) >> info->shift) & (BIT(info->width) - 1); +} + +int gpio_set_driving_adv(gpio_t gpio, enum gpio_drv_adv drv) +{ + uint32_t mask; + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg_adv; + + if (!is_valid_drv_adv(drv)) + return -1; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + + if (adv_info->width == 0) + return -1; + + /* Not include EH bit (the lowest bit) */ + if ((uint32_t)drv > (BIT(adv_info->width - 1) - 1)) + return -1; + + mask = BIT(adv_info->width) - 1; + /* EH enable */ + drv = (drv << 1) | BIT(0); + + clrsetbits32(reg_adv, mask << adv_info->shift, drv << adv_info->shift); + + return 0; +} + +int gpio_get_driving_adv(gpio_t gpio) +{ + const struct gpio_drv_info *adv_info = &gpio_driving_adv_info[gpio.id]; + void *reg_adv; + uint32_t drv; + + reg_adv = gpio_find_reg_addr(gpio) + adv_info->offset; + if (adv_info->width == 0) + return -1; + + drv = (read32(reg_adv) >> adv_info->shift) & (BIT(adv_info->width) - 1); + + /* Drop EH bit */ + return drv >> 1; +} diff --git a/src/soc/mediatek/mt8186/include/soc/gpio.h b/src/soc/mediatek/mt8186/include/soc/gpio.h index a47d27c..8a1c147 100644 --- a/src/soc/mediatek/mt8186/include/soc/gpio.h +++ b/src/soc/mediatek/mt8186/include/soc/gpio.h @@ -12,12 +12,25 @@ #include <soc/gpio_common.h> #include <types.h> +#define GPIO_NUM 185 + enum { MAX_GPIO_REG_BITS = 32, MAX_GPIO_MODE_PER_REG = 8, GPIO_MODE_BITS = 4, }; +enum gpio_drv { + GPIO_DRV_2_MA = 0, + GPIO_DRV_4_MA = 1, + GPIO_DRV_6_MA = 2, + GPIO_DRV_8_MA = 3, + GPIO_DRV_10_MA = 4, + GPIO_DRV_12_MA = 5, + GPIO_DRV_14_MA = 6, + GPIO_DRV_16_MA = 7, +}; + #define PIN(id, name, flag, bit, base, offset, \ func1, func2, func3, func4, func5, func6, func7) \ PAD_##name##_ID = id, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 16 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62466 ) Change subject: mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs ...................................................................... mb/google/brya/var/kano: Update TDP PL1, PL2, and PL4 for U28 SKUs Based on testing results from the thermal team, they have decided to update PL1, PL2 and PL4 for U28 SKUs. BUG=b:221338290 TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/ramstage.c 2 files changed, 17 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Ren Kuo: Looks good to me, approved EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 5fbeb3c..39cca42 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -63,6 +63,18 @@ }, }" + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + + register "power_limits_config[ADL_P_682_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 43, + .tdp_pl4 = 105, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -119,14 +131,14 @@ register "controls.power_limits" = "{ .pl1 = { .min_power = 18000, - .max_power = 28000, + .max_power = 20000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, }, .pl2 = { - .min_power = 40000, - .max_power = 40000, + .min_power = 43000, + .max_power = 43000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000, diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c index 9bba1df..aa48a9d 100644 --- a/src/mainboard/google/brya/variants/kano/ramstage.c +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -7,8 +7,8 @@ /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ { PCI_DID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, { PCI_DID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, - { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DID_INTEL_ADL_P_ID_5, 28, 18000, 20000, 43000, 43000, 105000 }, + { PCI_DID_INTEL_ADL_P_ID_3, 28, 18000, 20000, 43000, 43000, 105000 }, }; void variant_devtree_update(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/62466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c Gerrit-Change-Number: 62466 Gerrit-PatchSet: 6 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Alan Huang <alan-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/variants/felwinter: Fix stylus UI behavior bug
by Felix Held (Code Review) 09 Mar '22

09 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62638 ) Change subject: mb/google/brya/variants/felwinter: Fix stylus UI behavior bug ...................................................................... mb/google/brya/variants/felwinter: Fix stylus UI behavior bug Fix stylus UI behavior bug. 1) it appears the kernel's gpio_key driver is not expecting an IRQ descriptor for the `gpio` property, therefore change to an active-low input. 2) The wakeup event was configured backwards. Change list - Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW". - Change wakeup_event_action from ASSERTED to DEASSERTED. BUG=b:220992812 TEST=emerge-brya coreboot chromeos-bootimage and verify pass Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index d184276..acd96dd 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -275,10 +275,10 @@ end chip drivers/generic/gpio_keys register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A7)" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_A7)" register "key.wake_gpe" = "GPE0_DW0_08" register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" register "key.dev_name" = ""EJCT"" register "key.linux_code" = "SW_PEN_INSERTED" register "key.linux_input_type" = "EV_SW" 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2 Gerrit-Change-Number: 62638 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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