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Change subject: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
......................................................................
Patch Set 3: Code-Review+1
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Change subject: libpayload: Parse the ACPI RSDP table entry
......................................................................
Patch Set 6: Code-Review+2
(1 comment)
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/62576/comment/66110df4_0357751f
PS6, Line 271: info->acpi_rsdp = cb_unpack64(cb_acpi_rsdp->rsdp_pointer);
Thanks for the explanation.
> The basic problem is payloads like FILO that shift the whole segments and relocate themself this way. The payload copies itself to the new offset, so all global, "virtual" pointers that point inside the payload stay valid, but all that point outside the payload would have to be manually adjusted
I hadn't seen a payload which did that yet, looks like this is the relocate() function in x86/segment.c ?
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Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
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Change subject: mb/google/brya: Set EPP to 45% for all Brya variants
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62655/comment/4b833678_9dc784a3
PS4, Line 9: 45%
> Yes, this is the recommended EPP value for optimal power and performance based on ADL QS silicon.
Done
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Change subject: mb/google/brya: Set EPP to 45% for all Brya variants
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62655/comment/c1228f4d_7c2583f6
PS4, Line 9: 45%
> Did we end up deciding in 45%?
Yes, this is the recommended EPP value for optimal power and performance based on ADL QS silicon.
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Change subject: cpu/intel/common: Add support for energy performance preference (EPP)
......................................................................
cpu/intel/common: Add support for energy performance preference (EPP)
This provides support to update energy performance preference value.
BUG=b:219785001
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---
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M src/include/cpu/x86/msr.h
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Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
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Change subject: drivers/i2c/cs35l53: Add driver for generating device in SSDT
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
ping, anyone from cirrus logic able to continue on this or do you need some help?
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