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Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/62654/comment/cf988872_e03afd56
PS5, Line 131: Engery
Energy
Also I think the one print from pre_mp_init if it's not supported is enough
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Change subject: cpu/intel/common: Add support for energy performance preference (EPP)
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62653/comment/6f2924aa_ba59f73e
PS3, Line 12: BRANCH=firmware-brya-14505.Bre-brya-14505.B
nit:
`BRANCH=firmware-brya-14505.B`
you've got an extra half of it at the end
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Change subject: libpayload: Parse the ACPI RSDP table entry
......................................................................
Patch Set 6:
(1 comment)
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/62576/comment/b69eb207_29ec7f2e
PS6, Line 271: info->acpi_rsdp = cb_unpack64(cb_acpi_rsdp->rsdp_pointer);
> Technically shouldn't there be a virt_to_phys() call after unpacking?
We decided at some point that it's easier to only store physical addresses
in sysinfo. It's not beautiful but everything else we tried before degraded
at some point ;) The basic problem is payloads like FILO that shift the whole
segments and relocate themself this way. The payload copies itself to the
new offset, so all global, "virtual" pointers that point inside the payload
stay valid, but all that point outside the payload would have to be manually
adjusted. It's just easier to not have global pointers (or at least not
early on) that point outside the payload.
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Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62574/comment/9d45283c_0db8d7d5
PS6, Line 19: always is
> is always
Done
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Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
BRANCH=firmware-brya-14505.Bre-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
2 files changed, 26 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/5
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Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case
......................................................................
Patch Set 8: Code-Review+2
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Change subject: cpu/intel/common: Add support for energy performance preference (EPP)
......................................................................
Patch Set 3:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62653/comment/8955c816_0644515e
PS1, Line 7: src/cpu/intel/common
> `cpu/intel/common`
Done
https://review.coreboot.org/c/coreboot/+/62653/comment/4012d27a_dd9f6736
PS1, Line 12: BRANCH=firmware
: BRANCH=firmware-brya-14505.Bre-brya-14505.B
> `BRANCH=firmware-brya-14505. […]
Done
File src/cpu/intel/common/common_init.c:
https://review.coreboot.org/c/coreboot/+/62653/comment/e0be99de_dfdfbac8
PS1, Line 12: #define CPUID_6_ENGERY_PERF_PREF (1<<10)
: #define CPUID_6_HWP (1<<7)
> nit: make sure these all line up on the right side
Done
https://review.coreboot.org/c/coreboot/+/62653/comment/1d9958b9_2866180d
PS1, Line 212: HWP_ENABLE
> maybe a more informative message here, e.g. […]
Done
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/62653/comment/cf740f9a_721c9e92
PS1, Line 88: #define IA32_PM_ENABLE 0x770
: #define HWP_ENABLE 0x1
: #define IA32_HWP_CAPABILITIES 0x771
: #define IA32_HWP_REQUEST 0x774
: #define IA32_HWP_REQUEST_EPP_MASK 0xff000000
: #define IA32_HWP_REQUEST_EPP_SHIFT 24
> nit: make sure these all line up on the right side
Done
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Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62653
to look at the new patch set (#3).
Change subject: cpu/intel/common: Add support for energy performance preference (EPP)
......................................................................
cpu/intel/common: Add support for energy performance preference (EPP)
This provides support to update energy performance preference value.
BUG=b:219785001
BRANCH=firmware-brya-14505.Bre-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: I381bca6c7746a4ae7ca32aa1b4992a6d53c8eaaa
---
M src/cpu/intel/common/common.h
M src/cpu/intel/common/common_init.c
M src/include/cpu/x86/msr.h
3 files changed, 66 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62653/3
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Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62670 )
Change subject: mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
......................................................................
mb/google/guybrush: Enable DEBUG_SMI for non-serial firmware
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.
BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
---
M src/mainboard/google/guybrush/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/62670/1
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index ecec688..b2cba6e 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -13,6 +13,7 @@
select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384
select CONSOLE_CBMEM_DUMP_TO_UART if !CONSOLE_SERIAL
+ select DEBUG_SMI if !CONSOLE_SERIAL # TODO(b/217968734): Always enable
select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_ACPI_THERMAL_ZONE
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