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Hello Raul Rangel, Jon Murphy, Rob Barnes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62667
to look at the new patch set (#2).
Change subject: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
......................................................................
mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the power button.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/62667/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62374 )
Change subject: mb/google/brask/variants/moli: Reduce PSysMax to 11 A
......................................................................
Patch Set 9:
(1 comment)
File src/mainboard/google/brya/variants/moli/ramstage.c:
https://review.coreboot.org/c/coreboot/+/62374/comment/ebad8808_edf26bb6
PS9, Line 13: PCI_DEVICE_ID_INTEL_ADL_P_ID_10
this patch needs to be updated since CB:39331 landed in the meantime
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62667 )
Change subject: mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
......................................................................
mb/google/guybrush/var/nipperkin: Update privacy GPIO to Graphics DRM
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/62667/1
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index 776edc8..adde71f 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -187,7 +187,7 @@
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
register "device[0].privacy.enabled" = "1"
- register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_5)"
+ register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_18)"
device generic 0.0 on end
end
end
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Change subject: mb/dell/snb_ivb_workstations: Add Precision T1650 support
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/dell/optiplex_9010/sch5545_ec.c: Fix small bugs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/dell/optiplex_9010/sch5545_ec.c:
https://review.coreboot.org/c/coreboot/+/62210/comment/c7e89707_78621df3
PS1, Line 676: ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP);
This could probably use a better commit title than "fix small bugs"
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Change subject: mb/dell/optiplex_9010/mainboard.c: Add missing space
......................................................................
Patch Set 1: Code-Review+2
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62560 )
Change subject: soc/intel/common: Retry MEI CSE DISABLE command
......................................................................
Patch Set 3:
(3 comments)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/62560/comment/1f4f1aa9_de2977ff
PS3, Line 14: MAX_RETRY_EOP_MSG
> does it make sense to create enum as below, you can make this flexible to add short or long retry co […]
Hmm :) I don't think this will be required!
https://review.coreboot.org/c/coreboot/+/62560/comment/895d2050_5d137a59
PS3, Line 31: decode_heci_send_receive_error
> how this function is different than decode_eop_error() below? […]
Since EOP command handler returns cse_eop_result type enum values while CSE DISABLE command handler use generic cse_cmd_result enum values. hence, I used separate function for the same action. By using unified enum values for EOP and CSE DISABLE command handlers, then we can use common function that can be used for the both command handlers.
https://review.coreboot.org/c/coreboot/+/62560/comment/29fabb92_12438148
PS3, Line 77: cse_send_bus_disable_message
> it's almost same as cse_send_end_of_post_message() […]
See above reason. Both handlers use own enum values, so APIs return different enum type values. Hence, separate function is used. We can use common function by implementing the unified enum type values.
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