coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge
by Tim Wawrzynczak (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Felix Singer, Dtrain Hsu, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62631 ) Change subject: mb/google/brya/var/kinox: Enable PCIe-eMMC bridge ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec34708e5879c47f5339c48fd996eb6d7ef0ee86 Gerrit-Change-Number: 62631 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:25:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Tim Wawrzynczak (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62553 ) Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/brya/variants/kinox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62553/comment/652c64d1_e1a5b8cb PS8, Line 52: register "led_feature" = "0xe0" : register "customized_led0" = "0x23f" : register "customized_led2" = "0x028" Sorry I know this is not very clear, but I believe the 8111 uses the `customized_leds` register, whereas the r8125 uses the `customized_led0/2/led_feature` registers -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 8 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:22:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Update INTEL DENVERTON-NS SOC & HARCUVAR CRB Maintainers
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61209 ) Change subject: MAINTAINERS: Update INTEL DENVERTON-NS SOC & HARCUVAR CRB Maintainers ...................................................................... MAINTAINERS: Update INTEL DENVERTON-NS SOC & HARCUVAR CRB Maintainers Split entry, remove Michal Motyl and add Jeff Daly. Change-Id: Ie572d95c9dd85f59bc3fe47bb61bc6b6866fe4c3 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61209 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Reviewed-by: Jeff Daly <jeffd(a)silicom-usa.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 16 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Suresh Bellampalli: Looks good to me, but someone else must approve Jeff Daly: Looks good to me, but someone else must approve diff --git a/MAINTAINERS b/MAINTAINERS index a8d279c..07502ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -298,6 +298,14 @@ S: Odd Fixes F: src/mainboard/intel/d510mo/ +INTEL HARCUVAR_CRB MAINBOARD +M: Jeff Daly <jeffd(a)silicom-usa.com> +M: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> +M: Suresh Bellampalli <suresh.bellampalli(a)intel.com> +M: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> +S: Maintained +F: src/mainboard/intel/harcuvar/ + INTEL STRAGO MAINBOARD M: Hannah Williams <hannah.williams(a)intel.com> S: Supported @@ -584,15 +592,6 @@ F: src/drivers/intel/ F: src/include/cpu/intel/ -INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB -M: Suresh Bellampalli <suresh.bellampalli(a)intel.com> -M: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> -M: Michal Motyl <michalx.motyl(a)intel.com> -M: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> -S: Maintained -F: src/mainboard/intel/harcuvar/ -F: src/soc/intel/denverton_ns/ - INTEL FSP 1.1 M: Lee Leahy <leroy.p.leahy(a)intel.com> M: Huang Jin <huang.jin(a)intel.com> @@ -672,6 +671,14 @@ F: /src/soc/intel/braswell/ F: /src/vendorcode/intel/fsp/fsp1_1/braswell/ +INTEL DENVERTON-NS SOC +M: Jeff Daly <jeffd(a)silicom-usa.com> +M: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> +M: Suresh Bellampalli <suresh.bellampalli(a)intel.com> +M: Mariusz Szafranski <mariuszx.szafranski(a)intel.com> +S: Maintained +F: src/soc/intel/denverton_ns/ + INTEL TIGERLAKE SOC M: Tim Wawrzynczak <twawrzynczak(a)chromium.org> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/61209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie572d95c9dd85f59bc3fe47bb61bc6b6866fe4c3 Gerrit-Change-Number: 61209 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/common/firmware: Hook up adding 10GbE LAN firmware
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60877 ) Change subject: sb/intel/common/firmware: Hook up adding 10GbE LAN firmware ...................................................................... sb/intel/common/firmware: Hook up adding 10GbE LAN firmware Add ability to use ifdtool to add LAN firmware to image using Kconfig Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/common/firmware/Makefile.inc 2 files changed, 51 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 2de86de..45d8be8 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -146,6 +146,41 @@ depends on HAVE_EC_BIN default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/ec.bin" +config MAINBOARD_USES_IFD_10GBE_0_REGION + def_bool n + +config HAVE_10GBE_0_BIN + bool "Add 10GbE Firmware Region 0" + depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_10GBE_0_REGION + help + The 10GbE region firmware file for LAN device 0. + + Select this if you are going to use the 10GbE 0 region and have the + firmware. The firmware will be added to final image through ifdtool. + +config 10GBE_0_BIN_PATH + string "Path to 10GbE region 0 firmware" + depends on HAVE_10GBE_0_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/10gbe0.bin" + +config MAINBOARD_USES_IFD_10GBE_1_REGION + def_bool n + depends on MAINBOARD_USES_IFD_10GBE_0_REGION + +config HAVE_10GBE_1_BIN + bool "Add 10GbE Firmware Region 1" + depends on HAVE_IFD_BIN && MAINBOARD_USES_IFD_10GBE_1_REGION + help + The 10GbE region firmware file for LAN device 1. + + Select this if you are going to use the 10GbE 1 region and have the + firmware. The firmware will be added to final image through ifdtool. + +config 10GBE_1_BIN_PATH + string "Path to 10GbE region 1 firmware" + depends on HAVE_10GBE_1_BIN + default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/10gbe1.bin" + choice prompt "Protect flash regions" if HAVE_IFD_BIN default UNLOCK_FLASH_REGIONS if HAVE_IFD_BIN diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index 693bafb..ba1d3b1 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -86,7 +86,22 @@ -O $(obj)/coreboot.pre \ $(obj)/coreboot.pre endif - +ifeq ($(CONFIG_HAVE_10GBE_0_BIN),y) + printf " IFDTOOL 10gbe0.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i 10GbE_0:$(CONFIG_10GBE_0_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif +ifeq ($(CONFIG_HAVE_10GBE_1_BIN),y) + printf " IFDTOOL 10gbe1.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + -i 10GbE_1:$(CONFIG_10GBE_1_BIN_PATH) \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) printf " IFDTOOL Locking Management Engine\n" $(objutil)/ifdtool/ifdtool \ -- To view, visit https://review.coreboot.org/c/coreboot/+/60877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id45ab4b69a85a5f8e52c0c4b130b6d729222b4c3 Gerrit-Change-Number: 60877 Gerrit-PatchSet: 17 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/ifdtool: Add support for Denverton SoC
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60830 ) Change subject: util/ifdtool: Add support for Denverton SoC ...................................................................... util/ifdtool: Add support for Denverton SoC Denverton is a special version of IFD2 flash layout. It defines 10GbE firmware regions (11/12) and the IE (10) region which other IFD2 platforms do not have. Denverton does not include the legacy GbE region (3) or the EC region (8) which other IFD2 platforms do have. TEST='ifdtool -p dnv coreboot.rom' and verify correct output Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/denverton_ns/Kconfig M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 3 files changed, 77 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 194067a..8cf0754 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -174,4 +174,8 @@ endchoice +config IFD_CHIPSET + string + default "dnv" + endif ## SOC_INTEL_DENVERTON_NS diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 20c4ed4..a5c0b69 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -28,6 +28,22 @@ ((const char *)(ptr) >= (base) && \ (const char *)&(ptr)[1] <= (base) + (limit)) +/** + * PLATFORM_HAS_GBE_REGION - some platforms do not support the PCH GbE LAN region + */ +#define PLATFORM_HAS_GBE_REGION (platform != PLATFORM_DNV) + +/* + * PLATFORM_HAS_EC_REGION - some platforms do not support the EC region + */ +#define PLATFORM_HAS_EC_REGION (ifd_version >= IFD_VERSION_2 && platform != PLATFORM_DNV) + +/* + * PLATFORM_HAS_10GBE_X_REGION - some platforms have 1 or more 10GbE LAN regions + */ +#define PLATFORM_HAS_10GBE_0_REGION (platform == PLATFORM_DNV) +#define PLATFORM_HAS_10GBE_1_REGION (platform == PLATFORM_DNV) + static int ifd_version; static int chipset; static unsigned int max_regions = 0; @@ -237,6 +253,8 @@ return CHIPSET_400_SERIES_ICE_POINT; case PLATFORM_LBG: return CHIPSET_C620_SERIES_LEWISBURG; + case PLATFORM_DNV: + return CHIPSET_DENVERTON; default: return CHIPSET_PCH_UNKNOWN; } @@ -255,6 +273,7 @@ PLATFORM_GLK, PLATFORM_CNL, PLATFORM_LBG, + PLATFORM_DNV, PLATFORM_ICL, PLATFORM_TGL, PLATFORM_JSL, @@ -713,35 +732,55 @@ } /* EC region access only available on v2+ */ - if (ifd_version >= IFD_VERSION_2) + if (PLATFORM_HAS_EC_REGION) printf(" EC Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 8))) ? "enabled" : "disabled"); printf(" Platform Data Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 4))) ? "enabled" : "disabled"); - printf(" GbE Region Write Access: %s\n", - (flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled"); + if (PLATFORM_HAS_GBE_REGION) { + printf(" GbE Region Write Access: %s\n", + (flmstr & (1 << (wr_shift + 3))) ? "enabled" : "disabled"); + } printf(" Intel ME Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 2))) ? "enabled" : "disabled"); printf(" Host CPU/BIOS Region Write Access: %s\n", (flmstr & (1 << (wr_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Write Access: %s\n", (flmstr & (1 << wr_shift)) ? "enabled" : "disabled"); + if (PLATFORM_HAS_10GBE_0_REGION) { + printf(" 10GbE_0 Write Access: %s\n", + (flmstr & (1 << (wr_shift + 11))) ? "enabled" : "disabled"); + } + if (PLATFORM_HAS_10GBE_1_REGION) { + printf(" 10GbE_1 Write Access: %s\n", + (flmstr & (1 << 4)) ? "enabled" : "disabled"); + } - if (ifd_version >= IFD_VERSION_2) + if (PLATFORM_HAS_EC_REGION) printf(" EC Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 8))) ? "enabled" : "disabled"); printf(" Platform Data Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 4))) ? "enabled" : "disabled"); - printf(" GbE Region Read Access: %s\n", - (flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled"); + if (PLATFORM_HAS_GBE_REGION) { + printf(" GbE Region Read Access: %s\n", + (flmstr & (1 << (rd_shift + 3))) ? "enabled" : "disabled"); + } printf(" Intel ME Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 2))) ? "enabled" : "disabled"); printf(" Host CPU/BIOS Region Read Access: %s\n", (flmstr & (1 << (rd_shift + 1))) ? "enabled" : "disabled"); printf(" Flash Descriptor Read Access: %s\n", (flmstr & (1 << rd_shift)) ? "enabled" : "disabled"); + if (PLATFORM_HAS_10GBE_0_REGION) { + printf(" 10GbE_0 Read Access: %s\n", + (flmstr & (1 << (rd_shift + 11))) ? "enabled" : "disabled"); + } + if (PLATFORM_HAS_10GBE_1_REGION) { + printf(" 10GbE_1 Read Access: %s\n", + (flmstr & (1 << 0)) ? "enabled" : "disabled"); + } /* Requestor ID doesn't exist for ifd 2 */ if (ifd_version < IFD_VERSION_2) @@ -756,11 +795,16 @@ decode_flmstr(fmba->flmstr1); printf("FLMSTR2: 0x%08x (Intel ME)\n", fmba->flmstr2); decode_flmstr(fmba->flmstr2); - printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); - decode_flmstr(fmba->flmstr3); - if (ifd_version >= IFD_VERSION_2) { - printf("FLMSTR5: 0x%08x (EC)\n", fmba->flmstr5); - decode_flmstr(fmba->flmstr5); + if (PLATFORM_HAS_GBE_REGION) { + printf("FLMSTR3: 0x%08x (GbE)\n", fmba->flmstr3); + decode_flmstr(fmba->flmstr3); + if (ifd_version >= IFD_VERSION_2) { + printf("FLMSTR5: 0x%08x (EC)\n", fmba->flmstr5); + decode_flmstr(fmba->flmstr5); + } + } else { + printf("FLMSTR6: 0x%08x (IE)\n", fmba->flmstr6); + decode_flmstr(fmba->flmstr6); } } @@ -1223,6 +1267,18 @@ fmba->flmstr5 |= (1 << REGION_EC) << wr_shift; } break; + case PLATFORM_DNV: + /* CPU/BIOS can read descriptor and BIOS. */ + fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; + /* CPU/BIOS can write BIOS. */ + fmba->flmstr1 |= (1 << REGION_BIOS) << wr_shift; + /* ME can read descriptor and ME. */ + fmba->flmstr2 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr2 |= (1 << REGION_ME) << rd_shift; + /* ME can write ME. */ + fmba->flmstr2 |= (1 << REGION_ME) << wr_shift; + break; default: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; @@ -1642,6 +1698,7 @@ " aplk - Apollo Lake\n" " cnl - Cannon Lake\n" " lbg - Lewisburg PCH\n" + " dnv - Denverton\n" " ehl - Elkhart Lake\n" " glk - Gemini Lake\n" " icl - Ice Lake\n" @@ -1899,6 +1956,8 @@ platform = PLATFORM_CNL; } else if (!strcmp(optarg, "lbg")) { platform = PLATFORM_LBG; + } else if (!strcmp(optarg, "dnv")) { + platform = PLATFORM_DNV; } else if (!strcmp(optarg, "ehl")) { platform = PLATFORM_EHL; } else if (!strcmp(optarg, "glk")) { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 15e207d..67f31c3 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -45,6 +45,7 @@ CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) * variants onwards */ CHIPSET_C620_SERIES_LEWISBURG, + CHIPSET_DENVERTON, }; enum platform { @@ -59,6 +60,7 @@ PLATFORM_TGL, PLATFORM_ADL, PLATFORM_IFD2, + PLATFORM_DNV, }; #define LAYOUT_LINELEN 80 @@ -171,6 +173,7 @@ uint32_t flmstr3; uint32_t flmstr4; uint32_t flmstr5; + uint32_t flmstr6; } __attribute__((packed)) fmba_t; // processor strap -- To view, visit https://review.coreboot.org/c/coreboot/+/60830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523 Gerrit-Change-Number: 60830 Gerrit-PatchSet: 16 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: set up gpio
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62314 ) Change subject: mb/google/brask/variants/moli: set up gpio ...................................................................... mb/google/brask/variants/moli: set up gpio Set the GPIO configuration of moli BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> --- A src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/gpio.c 2 files changed, 155 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/moli/gpio.c b/src/mainboard/google/brya/variants/moli/gpio.c new file mode 100644 index 0000000..54406ff9 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/gpio.c @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A15 : USB_OC2# ==> DDIC_DP_HPD4 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), + /* A21 : DDPC_CTRCLK ==> DDIC_DP_CTRCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : DDPC_CTRLDATA ==> DDIC_DP_CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> EMMC_PERST_L */ + PAD_CFG_GPO(GPP_B3, 1, DEEP), + + /* C3 : SML0CLK ==> PCH_SML0_CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> PCH_SML0_DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC(GPP_D9, NONE), + /* D14 : ISH_UART0_TXD ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D16 : ISH_UART0_CTS# ==> USB_A2_RT_RST_ODL */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E1 : THC0_SPI1_IO2 ==> B2B_HDMICARD_DETN */ + PAD_CFG_GPI(GPP_E1, NONE, DEEP), + /* E2 : THC0_SPI1_IO3 ==> B2B_DPCARD_DETN */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E5, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> B2B_USBCCARD_DETN */ + PAD_NC(GPP_E12, NONE), + /* E13 : THC0_SPI1_IO2 ==> B2B_SERIAL_DETN */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E20 : DDP2_CTRLCLK ==> EN_PP3300_EMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E21 : DDP2_CTRLDATA ==> NC */ + PAD_NC(GPP_E21, NONE), + + /* H19 : SRCCLKREQ4# ==> LAN_I225V_CLKREQ_ODL */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), + + /* GPD11: LANPHYC ==> LAN_DISABLE_N */ + PAD_CFG_GPO(GPD11, 0, DEEP), +}; + + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 0, PLTRST), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* D18 : UART1_TXD ==> SD_PE_RST_L */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35 Gerrit-Change-Number: 62314 Gerrit-PatchSet: 12 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Disable ACPI support last when suspending
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62335 ) Change subject: ec/starlabs/merlin: Disable ACPI support last when suspending ...................................................................... ec/starlabs/merlin: Disable ACPI support last when suspending When entering suspend, ACPI support is disabled by setting OSFG to 0x00. This has been moved to be the final action, so it is after saving the current EC settings. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62335 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/suspend.asl 1 file changed, 10 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 2dae8da..f89e501 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -2,8 +2,6 @@ Method (RPTS, 1, NotSerialized) { - \_SB.PCI0.LPCB.EC.OSFG = 0x00 - If ((Arg0 == 0x04) || (Arg0 == 0x05)) { /* Store current EC settings in CMOS */ @@ -16,10 +14,20 @@ \_SB.PCI0.LPCB.KLBC = \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)) } + + /* + * Disable ACPI support. + * This should always be the last action before entering S4 or S5. + */ + \_SB.PCI0.LPCB.EC.OSFG = 0x00 } Method (RWAK, 1, Serialized) { + /* + * Enable ACPI support. + * This should always be the first action when exiting S4 or S5. + */ \_SB.PCI0.LPCB.EC.OSFG = 0x01 /* Restore EC settings from CMOS */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5705efab42d2fe0fd5abc6c17eeea46ead27db17 Gerrit-Change-Number: 62335 Gerrit-PatchSet: 7 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/starlabs/merlin: Use ECRD function
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62334 ) Change subject: ec/starlabs/merlin: Use ECRD function ...................................................................... ec/starlabs/merlin: Use ECRD function Use ECRD function, instead of getting raw values from emem, to avoid a lack of syncronisation as it uses a mutex. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/ac.asl M src/ec/starlabs/merlin/acpi/lid.asl M src/ec/starlabs/merlin/acpi/suspend.asl 3 files changed, 10 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/ec/starlabs/merlin/acpi/ac.asl b/src/ec/starlabs/merlin/acpi/ac.asl index 847f872e..01dcca9 100644 --- a/src/ec/starlabs/merlin/acpi/ac.asl +++ b/src/ec/starlabs/merlin/acpi/ac.asl @@ -9,7 +9,7 @@ } Method (_PSR, 0) { - PWRS = ECPS & 0x01 + PWRS = (ECRD (RefOf(ECPS)) & 0x01) Return (PWRS) } Method (_PCL, 0) diff --git a/src/ec/starlabs/merlin/acpi/lid.asl b/src/ec/starlabs/merlin/acpi/lid.asl index 936eeed..0eaa2c5 100644 --- a/src/ec/starlabs/merlin/acpi/lid.asl +++ b/src/ec/starlabs/merlin/acpi/lid.asl @@ -11,6 +11,6 @@ { // 0x00 == Closed // 0x01 == Open - Return (^^LSTE) + Return (ECRD (RefOf (LSTE))) } } diff --git a/src/ec/starlabs/merlin/acpi/suspend.asl b/src/ec/starlabs/merlin/acpi/suspend.asl index 08ca7871..2dae8da 100644 --- a/src/ec/starlabs/merlin/acpi/suspend.asl +++ b/src/ec/starlabs/merlin/acpi/suspend.asl @@ -7,10 +7,14 @@ If ((Arg0 == 0x04) || (Arg0 == 0x05)) { /* Store current EC settings in CMOS */ - \_SB.PCI0.LPCB.TPLC = \_SB.PCI0.LPCB.EC.TPLE - \_SB.PCI0.LPCB.FLKC = \_SB.PCI0.LPCB.EC.FLKE - \_SB.PCI0.LPCB.KLSC = \_SB.PCI0.LPCB.EC.KLSE - \_SB.PCI0.LPCB.KLBC = \_SB.PCI0.LPCB.EC.KLBE + \_SB.PCI0.LPCB.TPLC = + \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE)) + \_SB.PCI0.LPCB.FLKC = + \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)) + \_SB.PCI0.LPCB.KLSC = + \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)) + \_SB.PCI0.LPCB.KLBC = + \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/62334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31113ef9af3a1e171e3e1f226e7adcfa0fbce61b Gerrit-Change-Number: 62334 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62008 ) Change subject: drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address ...................................................................... drivers/intel/i210: Set log level to BIOS_NOTICE on missing MAC address Set the log level to BIOS_NOTICE for the case where the mainboard can not provide a MAC address since this can be a valid case. Showing this message with log level BIOS_ERR is not appropriate. In addition, rephrase the message to make clear that if the mainboard does not provide a MAC address the one stored in the MAC will be used. Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/intel/i210/i210.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 0b2fcd2..c63ae0e 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -187,7 +187,7 @@ /*Check first whether there is a valid MAC address available */ status = mainboard_get_mac_address(dev, adr_to_set); if (status != CB_SUCCESS) { - printk(BIOS_ERR, "I210: No valid MAC address found\n"); + printk(BIOS_NOTICE, "I210: Mainboard has no address, keep the one in MAC.\n"); return; } /* Before we will write a new address, check the existing one */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibfc58845f0ea47ced048b446e685c4860a29f075 Gerrit-Change-Number: 62008 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62585 ) Change subject: mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10 ...................................................................... mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10 When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for bluetooth. So update the nivviks overridetree to enable port 10 instead of port 8, which is the external port used for bluetooth with PCIe WLAN. BUG=b:222595137 TEST=Bluetooth works on nivviks Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Signed-off-by: Reka Norman <rekanorman(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb 3 files changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 91c633a..d85e230 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -25,7 +25,6 @@ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 diff --git a/src/mainboard/google/brya/variants/nereid/overridetree.cb b/src/mainboard/google/brya/variants/nereid/overridetree.cb index add5e21..9cb27e8 100644 --- a/src/mainboard/google/brya/variants/nereid/overridetree.cb +++ b/src/mainboard/google/brya/variants/nereid/overridetree.cb @@ -13,6 +13,7 @@ register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN device domain 0 on device ref i2c1 on diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 194b26f..8ccbac7 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -12,6 +12,8 @@ register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + device domain 0 on device ref ipu on chip drivers/intel/mipi_camera @@ -300,7 +302,7 @@ register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" - device ref usb2_port8 on end + device ref usb2_port10 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" -- To view, visit https://review.coreboot.org/c/coreboot/+/62585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864 Gerrit-Change-Number: 62585 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kangheui Won <khwon(a)chromium.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2022