coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Werner Zeh (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Lean Sheng Tan, Angel Pons, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/62566/comment/32cc1cdd_9234b1b1 PS2, Line 164: MP_SERVICES_PPI > but after cherry picking your CL, it become dead slow. Hmmm, This is now totally unexpected. Which platform do you test? As I wrote already the sluggishness seems to be caused by the MEASURED_BOOT stuff, so without it being enabled I see way better times. Still investigating what happens there exactly. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:55:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Subrata Banik (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Lean Sheng Tan, Werner Zeh, Angel Pons, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/62566/comment/5bd81b82_b7e31fae PS2, Line 164: MP_SERVICES_PPI > Could you elaborate a bit more on this? At which time did you output this log? Right after the call to 'mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL)' or before? Please ignore my last comment, I had took earlier snapshot, I could see the ROM is not cached with ToT as well (but I don't see the sluggishness) [DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB [DEBUG] 0x00003fff80000800: PHYMASK0: Length = 0x0000000080000000, Valid [DEBUG] 0x0000000077000000: PHYBASE1: Address = 0x0000000077000000, UC [DEBUG] 0x00003fffff000800: PHYMASK1: Length = 0x0000000001000000, Valid [DEBUG] 0x0000000078000000: PHYBASE2: Address = 0x0000000078000000, UC [DEBUG] 0x00003ffff8000800: PHYMASK2: Length = 0x0000000008000000, Valid [DEBUG] 0x0000000090000001: PHYBASE3: Address = 0x0000000090000000, WC [DEBUG] 0x00003ffff0000800: PHYMASK3: Length = 0x0000000010000000, Valid [DEBUG] 0x0000000100000006: PHYBASE4: Address = 0x0000000100000000, WB [DEBUG] 0x00003fff00000800: PHYMASK4: Length = 0x0000000100000000, Valid [DEBUG] 0x0000000200000006: PHYBASE5: Address = 0x0000000200000000, WB [DEBUG] 0x00003fff80000800: PHYMASK5: Length = 0x0000000080000000, Valid [DEBUG] 0x000000027fc00000: PHYBASE6: Address = 0x000000027fc00000, UC [DEBUG] 0x00003fffffc00800: PHYMASK6: Length = 0x0000000000400000, Valid [DEBUG] 0x0000000000000000: PHYBASE7 [DEBUG] 0x0000000000000000: PHYMASK7: Disabled [DEBUG] 0x0000000000000000: PHYBASE8 [DEBUG] 0x0000000000000000: PHYMASK8: Disabled [DEBUG] 0x0000000000000000: PHYBASE9 [DEBUG] 0x0000000000000000: PHYMASK9: Disabled but after cherry picking your CL, it become dead slow. -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:50:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by Michał Żygowski (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Tim Crawford, Jeremy Soller, Tim Wawrzynczak, Michał Kopeć, Michael Niewöhner. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 3: (2 comments) Patchset: PS1: > So are you folks still interested in updating CB:57034 with something similar to what's in your fork […] We uploaded this patch totally aware of the other ones lurking on gerrit... The other patches didn't fully work in our case that is why we wanted to push this one as a reference for further work and unify the Optimus support once and for all. The final intent was to abandon the patch when the right implementation lands in. File src/drivers/gfx/nvidia/optimus/optimus.c: https://review.coreboot.org/c/coreboot/+/62496/comment/2c3563aa_83a95d46 PS3, Line 195: if (config->enable_gpio.pin_count) { > A GC6 compliant driver must be able to handle the JT DSM methods and decide to skip turning off powe […] Understood. We didn't implement the GC6 support because we haven't had any specification, expertise and methods to properly implement, yet verify the feature is working as supposed to. Additionally, you mentioned on OSFC that the vendor ACPI code for GC6 is dead, what forced us to leave the driver at the point shown in this patch (ported PCIe RTD3 driver to be as close to vendor ACPI as possible). The advantage is that the patch works under Linux and Windows (although it will simply turn the dGPU on and off as you implicitly said). In the other comment Tim mentioned you got hands on the hardware design guide which let you implement GC6 support. We would like to get rid of the multiplication of the Nvidia driver patches, so I hope we may work together on your Nvidia patchset to get it landed in coreboot tree. We intended to abandon this patch anways, since it is pretty much similar to CB:43615 in terms of ACPI code (back when we developed the Nvidia support, it was still an active patch). -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:37:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Jeremy Soller <jeremy(a)system76.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Johnny Li (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Raihow Shi, Felix Held. Johnny Li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 24: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62321/comment/cd51cab2_bbfbd7d4 PS22, Line 2: field OB 3 4 : option HDMI 0 : option DP 1 : end > I think we need to discuss the FW_CONFIG bit assignment in the b/215806030. […] Hi Zhuohao Yes, we will list and discuss the FW_CONFIG bit assignment in the b/215806030. -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 24 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:27:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 14: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/b888075e_42cc7834 PS12, Line 418: > I don't think we need to add these configs. […] Sorry, wrong CL link, it should be: https://review.coreboot.org/c/coreboot/+/56794/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:20:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 14: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/7fde1f65_23f8e408 PS12, Line 409: config PCI_MAP_BUS > Shouldn't this select PCI_COMMON too? Indeed, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:18:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#15). Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... libpayload/pci: Add PCIe interfaces for MediaTek platform Add PCIe configuration interfaces for MediaTek platform. The register base address of PCIe hardware might be different when it's a non-x86 platform, add 'pci_update_hw_base()' interface for users to update its base address to access PCIe hardware correctly. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c M payloads/libpayload/include/pci.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#14). Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... libpayload/pci: Split PCI interfaces as common and chip related Move the common APIs to pci_common.c and others to the chip related file. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc C payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 103 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 13: (1 comment) File payloads/libpayload/Kconfig: https://review.coreboot.org/c/coreboot/+/56789/comment/4e772d89_5e355c3e PS12, Line 418: > Similar to coreboot's implementation, could we add ECAM_MMCONF_SUPPORT and ECAM_MMCONF_BASE_ADDRESS? I don't think we need to add these configs. For Intel platform, pci_io_ops.c will be used, and it already has the register information which the x86 platform is needed. For other platforms(e.g. Mediatek) which does not support ECAM, they should provide 'pci_map_bus()' function like coreboot did to get the address of each device's config space, all they need is the register base address of PCIe hardware(CL:56794). I think maybe we can define this address or pass this information from the users(e.g. depthcharge). Is that okay for you, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 12:14:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: turn off WWAN DPR
by Kevin Chiu (Code Review) 08 Mar '22

08 Mar '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62663 ) Change subject: mb/google/guybrush/var/nipperkin: turn off WWAN DPR ...................................................................... mb/google/guybrush/var/nipperkin: turn off WWAN DPR Sets GPIO 42 to low to turn off WWAN DPR BUG=b:216735313 BRANCH=guybrush TEST=emerge-guybrush coreboot make sure GPIO42 is low Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62663/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index 0b3b9b2..0fdedbf 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -37,6 +37,8 @@ PAD_GPO(GPIO_18, HIGH), /* SOC_SC_PWRSV */ PAD_GPO(GPIO_31, HIGH), + /* WWAN_DPR_SAR_ODL */ + PAD_GPO(GPIO_42, HIGH), }; static const struct soc_amd_gpio override_early_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/62663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba Gerrit-Change-Number: 62663 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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