coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Subrata Banik (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: Please split this CL into two parts 1. First CL to add `debug` driver and `debug` can also move into `common/basecode`? common/block is for IP code. 2. CSE code use the debug driver provided APIs and select SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE kconfig inside SOC_INTEL_CSE_LITE_SKU config. -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Yu-Ping Wu, Jianjun Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56789 ) Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... Patch Set 13: (1 comment) File payloads/libpayload/drivers/pci_map_bus_ops.c: PS12: > Based on Shelly's design doc [1], should we call this pci_mmio_ops.c? […] I think `pci_mmio_ops.c` corresponds to ECAM. I like the current filename. -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:57:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Yu-Ping Wu, Jianjun Wang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/83c847f1_89a004d9 PS9, Line 14: 100ms > > > Something to keep in mind is that it only works as expected if `COLLECT_TIMESTAMPS` is enabled, but it's only `default y if ARCH_X86`. > > > > COLLECT_TIMESTAMPS is enabled for ChromeOS (src/vendorcode/google/chromeos/Kconfig). > > The code in mt8195/cherry should still work even if not built for chromeos. I wonder if we have some common approach for sharing data across stages? I agree. Maybe we could enable `COLLECT_TIMESTAMPS` by default on Mediatek platforms. As this option is user-controllable (it has a prompt), I wouldn't use a `select` statement but `default y` instead. As for sharing data across stages, I think the CBMEM_INIT hook stuff is the only common thing we have. > > I think an implementation of `timestamp_get()` is needed for this to work. > > I agree, although we cannot use the name "timestamp_get" because it already exists for getting the timestamp. Maybe timestamp_find(id)? Alternatively, even better we could rename the current timestamp_get() to timestamp_now(). I meant to say that the `timestamp_get()` function has a __weak definition, which might have to be overriden. However, if `HAVE_MONOTONIC_TIMER` is enabled, it should work. For the new function, I'd also use the `timestamp_find(id)` name. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:55:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Subrata Banik (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:55:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs
by Subrata Banik (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jamie Ryu, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62581 ) Change subject: soc/intel/common: Include Meteor Lake device IDs ...................................................................... Patch Set 6: Code-Review+2 (2 comments) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/62581/comment/5f157890_7d6fad6b PS1, Line 3431: #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9 0x7e4d : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10 0x7eca : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11 0x7ecb : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12 0x7ecc > There is no CPU RPs in MTL. All RPs are in SOC/IOE die and FSP UPD is using same array for RP1- RP12;FSP handles like PCH RPs. > > So, We can use like below based on location. > PCI_DEVICE_ID_INTEL_MTP_SOC_PCIE_RP1-9 > PCI_DEVICE_ID_INTEL_MTP_IOE_P_PCIE_RP10-12 Got it, yes this align with EDS as well. So, with MTL, we are reducing the RPs from 16 (12 PCH and 4 CPU) to 12 (alone). can we rename the macro to reflect the MTL SoC block diagram proper as something like this: PCI_DEVICE_ID_INTEL_MTP_SOC_PCIE_RP1-9 PCI_DEVICE_ID_INTEL_MTP_IOE_P_PCIE_RP1-3 https://review.coreboot.org/c/coreboot/+/62581/comment/bc892f7a_79baa0d3 PS1, Line 3962: #define PCI_DEVICE_ID_INTEL_SIMICS_GT0 0xffff > It's used for report platform for early SOC without IGD. > We'll define and use in soc folder. what is the value of showing something that is 0xffff -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 6 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:54:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control coreboot and Intel SoC features
by Maulik V Vaghela (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Nico Huber, Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61380 ) Change subject: soc/intel/common: Add support to control coreboot and Intel SoC features ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62 Gerrit-Change-Number: 61380 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:53:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable dynamic debug capability for brya family
by Maulik V Vaghela (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61381 ) Change subject: mb/google/brya: Enable dynamic debug capability for brya family ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Gerrit-Change-Number: 61381 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable dynamic debug capability for brya family
by Sridhar Siricilla (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Paul Menzel, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61381 ) Change subject: mb/google/brya: Enable dynamic debug capability for brya family ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61381/comment/1a61d250_03cec5e2 PS12, Line 7: Enables > Enable Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Gerrit-Change-Number: 61381 Gerrit-PatchSet: 13 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:53:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/google/chromeos/Kconfig: Fix typo
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62661 ) Change subject: vc/google/chromeos/Kconfig: Fix typo ...................................................................... vc/google/chromeos/Kconfig: Fix typo heirarchy ---> hierarchy Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/62661/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 605b09e..780344c 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -46,7 +46,7 @@ default y depends on TPM2 && RESUME_PATH_SAME_AS_BOOT help - Disable the platform heirarchy on resume path if the firmware + Disable the platform hierarchy on resume path if the firmware is involved in resume. The hierarchy is disabled prior to jumping to the OS. Note that this option is sepcific to TPM2 boards. This option is auto selected if CHROMEOS because it matches with -- To view, visit https://review.coreboot.org/c/coreboot/+/62661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4 Gerrit-Change-Number: 62661 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/block/cse: Add option to send EOP early via SoC
by Maulik V Vaghela (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Sridhar Siricilla, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60195 to look at the new patch set (#12). Change subject: intel/common/block/cse: Add option to send EOP early via SoC ...................................................................... intel/common/block/cse: Add option to send EOP early via SoC Earlier while trying to optimize boot time End Of Post (EOP) time kept increasing (~80 ms) when boot time decreased to around 1 second. This was because CSE was busy with own firmware loading. When EOP was moved later in boot stage it again created issue since CSE got busy with other payload loading for OS boot, so response to EOP got delayed by ~70-80 ms. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya QS board. Since this setting might vary for each SoC, SoCs can decide when to send EOP in the boot sequence. This patch adds Kconfig option to send EOP via SoC BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Code compilation is fine for Brya board. Boot time test is done using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms. Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/60195/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/60195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35 Gerrit-Change-Number: 60195 Gerrit-PatchSet: 12 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravindra N <ravindra(a)intel.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022