coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Maulik V Vaghela (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Sridhar Siricilla. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62272 ) Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... Patch Set 9: (2 comments) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/62272/comment/9b5356ed_1b824acd PS7, Line 105: select SOC_INTEL_CSE_SEND_EOP_EARLY > move this above SOC_INTEL_CSE_SET_EOP Ack File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/62272/comment/b0b420d2_0c132c33 PS7, Line 162: if(CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) { > > space required before the open parenthesis '(' […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:30:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62472 ) Change subject: soc/mediatek/mt8186: set pin drive strength to 8mA for NOR ...................................................................... Patch Set 17: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a Gerrit-Change-Number: 62472 Gerrit-PatchSet: 17 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marina Michelle <marinamichelle100(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:30:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Angel Pons (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 15: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 15 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:29:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Send EOP early in the boot sequence
by Maulik V Vaghela (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla. Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62272 to look at the new patch set (#8). Change subject: soc/intel/adl: Send EOP early in the boot sequence ...................................................................... soc/intel/adl: Send EOP early in the boot sequence As part of boot time optimization, one of the culprit was CSE where response to End Of Post (EOP) command used to take ~60ms. Earlier patch was pushed to delay the EOP to reduce response time to ~5-7 ms. During this stage overall platform boot time was ~1.15 seconds. Once boot time was optimized to ~ 1 seconds, CSE EOP time again increased to ~80 ms since coreboot used to send EOP at the time where CSE was busy. This created some back and forth moving of sending EOP command function within coreboot sequence. Upon debugging using traces, it was found that coreboot used to send EOP late where CSE was busy loading other IP payload, so it might take more time to respond. In order to avoid delayed response, coreboot has to send EOP in stage when CSE is done with firmware init and it will be ready to serve EOP as soon as possible. This also aligns with previous flow where FSP used to send EOP once silicon init is done and coreboot used to rely on FSP to send this message. Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time reduces from ~60 ms to ~20 ms on Brya board. Note that once SoC code sends EOP, coreboot common code won't send it again since common code already has check in case EOP is sent earlier. BUG=b:211085685 BRANCH=firmware-brya-14505.B TEST=Tested on Brya system before and after the changes. Observed ~40ms savings in boot time. Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62272/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b Gerrit-Change-Number: 62272 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: docs/contributing/gsoc: Add project proposal template
by Felix Singer (Code Review) 08 Mar '22

08 Mar '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62659 ) Change subject: docs/contributing/gsoc: Add project proposal template ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/62659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d565ba4bcd56acb88916b0a93f59121d04fb570 Gerrit-Change-Number: 62659 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:12:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs
by Wonkyu Kim (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62581 ) Change subject: soc/intel/common: Include Meteor Lake device IDs ...................................................................... Patch Set 3: (21 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62581/comment/475c64c8_3d9e031b PS1, Line 7: Meteorlake > Meteor Lake ? Ack https://review.coreboot.org/c/coreboot/+/62581/comment/48a11969_4b920a3d PS1, Line 9: Meteorlake > Meteor Lake Ack https://review.coreboot.org/c/coreboot/+/62581/comment/6003189f_f82bb057 PS1, Line 9: vol1(640228) > Please add a space before the (. Ack File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/62581/comment/623078ec_1e1d57aa PS1, Line 3078: PCI_DEVICE_ID_INTEL_MTL_ESPI_0 > This is what EDS is saying, do we need to add all of these […] Currently we assigned 8 values for MTL M and P but they're not in external document. We'll add only assigned values to optimize common driver and add more once it's assigned. https://review.coreboot.org/c/coreboot/+/62581/comment/8c2d0ed6_9adbe890 PS1, Line 3431: #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9 0x7e4d : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10 0x7eca : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11 0x7ecb : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12 0x7ecc > I have some confusion here […] There is no CPU RPs in MTL. All RPs are in SOC/IOE die and FSP UPD is using same array for RP1- RP12;FSP handles like PCH RPs. So, We can use like below based on location. PCI_DEVICE_ID_INTEL_MTP_SOC_PCIE_RP1-9 PCI_DEVICE_ID_INTEL_MTP_IOE_P_PCIE_RP10-12 https://review.coreboot.org/c/coreboot/+/62581/comment/e4f46900_5f5b4104 PS1, Line 3508: #define PCI_DEVICE_ID_INTEL_MTL_SATA_2 0x7e67 : #define PCI_DEVICE_ID_INTEL_MTL_SATA_3 0x282a > you don't need these DID as for RAID mode. […] Ack https://review.coreboot.org/c/coreboot/+/62581/comment/4ebb913f_f685098f PS1, Line 3531: PCI_DEVICE_ID_INTEL_MTL_PMC > meaningful would be have different name macro […] Ack https://review.coreboot.org/c/coreboot/+/62581/comment/e1cfec51_ea431345 PS1, Line 3532: PCI_DEVICE_ID_INTEL_MTL_M_PMC > nit: PCI_DEVICE_ID_INTEL_MTL_M_IOE_PMC Ack https://review.coreboot.org/c/coreboot/+/62581/comment/88c4dcac_ca7adfbb PS1, Line 3533: PCI_DEVICE_ID_INTEL_MTL_P_PMC > nit: PCI_DEVICE_ID_INTEL_MTL_P_IOE_PMC Ack https://review.coreboot.org/c/coreboot/+/62581/comment/e6377b75_fead5e7a PS1, Line 3807: PCI_DEVICE_ID_INTEL_MTL_SPI0 > suggestion: […] Ack https://review.coreboot.org/c/coreboot/+/62581/comment/d0626fc9_ad7fe79f PS1, Line 3962: #define PCI_DEVICE_ID_INTEL_SIMICS_GT0 0xffff > u don't need this. no probing is done for 0xFFFF DID device. It's used for report platform for early SOC without IGD. We'll define and use in soc folder. https://review.coreboot.org/c/coreboot/+/62581/comment/bc7ffe62_0c40c225 PS1, Line 4140: PCI_DEVICE_ID_INTEL_MTL_M_XHCI > PCI_DEVICE_ID_INTEL_MTL_M_TCSS_XHCI Ack https://review.coreboot.org/c/coreboot/+/62581/comment/5142f76a_e0382e06 PS1, Line 4141: PCI_DEVICE_ID_INTEL_MTL_P_XHCI > same Ack https://review.coreboot.org/c/coreboot/+/62581/comment/6a3dc4ce_b57d62d5 PS1, Line 4163: PCI_DEVICE_ID_INTEL_MTL_P2SB > please follow the same suggestion as PMC DID and split between SOC and IOE Ack https://review.coreboot.org/c/coreboot/+/62581/comment/f3e05c63_b5abf713 PS1, Line 4178: PCI_DEVICE_ID_INTEL_MTL_SRAM > same as above Ack https://review.coreboot.org/c/coreboot/+/62581/comment/afdd3ccc_7f6a7e0c PS1, Line 4269: #define PCI_DEVICE_ID_INTEL_MTL_CSE1 0x7e71 : #define PCI_DEVICE_ID_INTEL_MTL_CSE2 0x7e74 : #define PCI_DEVICE_ID_INTEL_MTL_CSE3 0x7e75 > wondering, if we really need these HECI devices, we are keeping HECI1 alone enable. […] Ack https://review.coreboot.org/c/coreboot/+/62581/comment/c8e30cfb_807c6f63 PS1, Line 4292: PCI_DEVICE_ID_INTEL_MTL_M_XDCI > Please add _TCSS_ in between Ack https://review.coreboot.org/c/coreboot/+/62581/comment/8f5be521_a9253150 PS1, Line 4416: > can you please add CNVI Ids as well? Ack https://review.coreboot.org/c/coreboot/+/62581/comment/5400fa78_66cb316b PS1, Line 4424: > can you please add Crashlog ID as well? Ack File src/soc/intel/common/block/cpu/mp_init.c: https://review.coreboot.org/c/coreboot/+/62581/comment/b549bab7_f2a29193 PS1, Line 31: CPUID_METEORLAKE_1_A0 > suggestion: […] Ack File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/62581/comment/457345f5_6a842bfe PS2, Line 1291: PCI_DID_INTEL_ADP_M_CSE3, This is missing. -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 09:06:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs
by Wonkyu Kim (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jamie Ryu, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Jamie Ryu, Ethan Tsao, Subrata Banik, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62581 to look at the new patch set (#3). Change subject: soc/intel/common: Include Meteor Lake device IDs ...................................................................... soc/intel/common: Include Meteor Lake device IDs Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a --- M src/drivers/intel/ish/ish.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 25 files changed, 173 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62581/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 3 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs
by build bot (Jenkins) (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jamie Ryu, Ethan Tsao, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62581 ) Change subject: soc/intel/common: Include Meteor Lake device IDs ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/sram/sram.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143473): https://review.coreboot.org/c/coreboot/+/62581/comment/07abc730_054cd0c0 PS2, Line 39: PCI_DID_INTEL_MTL_CRASHLOG_SRAM, trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 08:58:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Hung-Te Lin (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/9b129a12_417ae9b9 PS9, Line 14: 100ms > > Something to keep in mind is that it only works as expected if `COLLECT_TIMESTAMPS` is enabled, but it's only `default y if ARCH_X86`. > > COLLECT_TIMESTAMPS is enabled for ChromeOS (src/vendorcode/google/chromeos/Kconfig). The code in mt8195/cherry should still work even if not built for chromeos. I wonder if we have some common approach for sharing data across stages? -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 08:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Meteor Lake device IDs
by Wonkyu Kim (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jamie Ryu, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Jamie Ryu, Ethan Tsao, Subrata Banik, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62581 to look at the new patch set (#2). Change subject: soc/intel/common: Include Meteor Lake device IDs ...................................................................... soc/intel/common: Include Meteor Lake device IDs Reference: chapter2 in Meteor Lake EDS vol1 (640228) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a --- M src/drivers/intel/ish/ish.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cnvi/cnvi.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/usb4/xhci.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 25 files changed, 173 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62581/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022