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Change in coreboot[master]: ec/starlabs: Guard Max Charge in Kconfig
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62123 ) Change subject: ec/starlabs: Guard Max Charge in Kconfig ...................................................................... ec/starlabs: Guard Max Charge in Kconfig Guard Max Charge EC write in Kconfig so it's only used on platforms that support it. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Andy Pont <andy.pont(a)sdcsystems.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/Kconfig M src/ec/starlabs/merlin/ec.c M src/mainboard/starlabs/labtop/Kconfig 3 files changed, 14 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Andy Pont: Looks good to me, but someone else must approve diff --git a/src/ec/starlabs/merlin/Kconfig b/src/ec/starlabs/merlin/Kconfig index 67582ac..93101b7 100644 --- a/src/ec/starlabs/merlin/Kconfig +++ b/src/ec/starlabs/merlin/Kconfig @@ -44,6 +44,13 @@ help Select if the mainboard has a fan. +config EC_STARLABS_MAX_CHARGE + bool + default n + depends on EC_STARLABS_ITE + help + Select if the mainboard supports limiting the maximum charge of the battery. + config EC_STARLABS_MERLIN bool "Use open-source Merlin EC Firmware" default n diff --git a/src/ec/starlabs/merlin/ec.c b/src/ec/starlabs/merlin/ec.c index 40be138..e8eaa22 100644 --- a/src/ec/starlabs/merlin/ec.c +++ b/src/ec/starlabs/merlin/ec.c @@ -130,11 +130,12 @@ CHARGE_60 }; - ec_write(ECRAM_MAX_CHARGE, - get_ec_value_from_option("max_charge", - 0, - max_charge, - ARRAY_SIZE(max_charge))); + if (CONFIG(EC_STARLABS_MAX_CHARGE)) + ec_write(ECRAM_MAX_CHARGE, + get_ec_value_from_option("max_charge", + 0, + max_charge, + ARRAY_SIZE(max_charge))); /* * Fan Mode diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig index 1700fb1..9bf4273 100644 --- a/src/mainboard/starlabs/labtop/Kconfig +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -31,6 +31,7 @@ select DRIVERS_INTEL_USB4_RETIMER select EC_STARLABS_KBL_LEVELS select EC_STARLABS_FAN + select EC_STARLABS_MAX_CHARGE select EC_STARLABS_NEED_ITE_BIN select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a Gerrit-Change-Number: 62123 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: timestamps: Rename timestamps to make names more consistent
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62019 ) Change subject: timestamps: Rename timestamps to make names more consistent ...................................................................... timestamps: Rename timestamps to make names more consistent This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/arch/arm64/romstage.c M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/commonlib/include/commonlib/timestamp_serialized.h M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/fsp_util.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/vpd/vpd.c M src/lib/bootblock.c M src/lib/cbfs.c M src/lib/decompressor.c M src/lib/fit_payload.c M src/lib/hardwaremain.c M src/lib/prog_loaders.c M src/lib/selfboot.c M src/mainboard/google/daisy/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/peach_pit/romstage.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/haswell/haswell_mrc/raminit.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/ironlake/romstage.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/x4x/raminit.c M src/security/vboot/ec_sync.c M src/security/vboot/vboot_loader.c M src/security/vboot/vboot_logic.c M src/soc/amd/cezanne/romstage.c M src/soc/amd/common/block/apob/apob_cache.c M src/soc/amd/common/pi/agesawrapper.c M src/soc/amd/picasso/romstage.c M src/soc/amd/sabrina/romstage.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/raminit.c M src/soc/intel/common/block/cse/cse_eop.c M src/southbridge/intel/bd82x6x/early_me.c M src/vendorcode/google/chromeos/cr50_enable_update.c M tests/lib/timestamp-test.c 52 files changed, 276 insertions(+), 276 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, but someone else must approve diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c index f4b4544..b144f93 100644 --- a/src/arch/arm64/romstage.c +++ b/src/arch/arm64/romstage.c @@ -12,7 +12,7 @@ void main(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 1df8c44..b07b512 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -30,7 +30,7 @@ if (!cbmem_online()) cbmem_initialize(); - timestamp_add_now(TS_START_POSTCAR); + timestamp_add_now(TS_POSTCAR_START); display_mtrrs(); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 8a5f902..2609fd6 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -192,7 +192,7 @@ load_postcar_cbfs(&prog, pcf); /* As postcar exist, it's end of romstage here */ - timestamp_add_now(TS_END_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_END); console_time_report(); diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 492508e..a51b68f 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -19,23 +19,23 @@ } __packed; enum timestamp_id { - TS_START_ROMSTAGE = 1, - TS_BEFORE_INITRAM = 2, - TS_AFTER_INITRAM = 3, - TS_END_ROMSTAGE = 4, - TS_START_VBOOT = 5, - TS_END_VBOOT = 6, - TS_START_COPYRAM = 8, - TS_END_COPYRAM = 9, - TS_START_RAMSTAGE = 10, - TS_START_BOOTBLOCK = 11, - TS_END_BOOTBLOCK = 12, - TS_START_COPYROM = 13, - TS_END_COPYROM = 14, - TS_START_ULZMA = 15, - TS_END_ULZMA = 16, - TS_START_ULZ4F = 17, - TS_END_ULZ4F = 18, + TS_ROMSTAGE_START = 1, + TS_INITRAM_START = 2, + TS_INITRAM_END = 3, + TS_ROMSTAGE_END = 4, + TS_VBOOT_START = 5, + TS_VBOOT_END = 6, + TS_COPYRAM_START = 8, + TS_COPYRAM_END = 9, + TS_RAMSTAGE_START = 10, + TS_BOOTBLOCK_START = 11, + TS_BOOTBLOCK_END = 12, + TS_COPYROM_START = 13, + TS_COPYROM_END = 14, + TS_ULZMA_START = 15, + TS_ULZMA_END = 16, + TS_ULZ4F_START = 17, + TS_ULZ4F_END = 18, TS_DEVICE_ENUMERATE = 30, TS_DEVICE_CONFIGURE = 40, TS_DEVICE_ENABLE = 50, @@ -50,8 +50,8 @@ TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, - TS_START_POSTCAR = 100, - TS_END_POSTCAR = 101, + TS_POSTCAR_START = 100, + TS_POSTCAR_END = 101, TS_DELAY_START = 110, TS_DELAY_END = 111, TS_READ_UCODE_START = 112, @@ -60,67 +60,67 @@ TS_ELOG_INIT_END = 115, /* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */ - TS_START_COPYVER = 501, - TS_END_COPYVER = 502, - TS_START_TPMINIT = 503, - TS_END_TPMINIT = 504, - TS_START_VERIFY_SLOT = 505, - TS_END_VERIFY_SLOT = 506, - TS_START_HASH_BODY = 507, - TS_DONE_LOADING = 508, - TS_DONE_HASHING = 509, - TS_END_HASH_BODY = 510, - TS_START_TPMPCR = 511, - TS_END_TPMPCR = 512, - TS_START_TPMLOCK = 513, - TS_END_TPMLOCK = 514, - TS_START_EC_SYNC = 515, + TS_COPYVER_START = 501, + TS_COPYVER_END = 502, + TS_TPMINIT_START = 503, + TS_TPMINIT_END = 504, + TS_VERIFY_SLOT_START = 505, + TS_VERIFY_SLOT_END = 506, + TS_HASH_BODY_START = 507, + TS_LOADING_END = 508, + TS_HASHING_END = 509, + TS_HASH_BODY_END = 510, + TS_TPMPCR_START = 511, + TS_TPMPCR_END = 512, + TS_TPMLOCK_START = 513, + TS_TPMLOCK_END = 514, + TS_EC_SYNC_START = 515, TS_EC_HASH_READY = 516, TS_EC_POWER_LIMIT_WAIT = 517, - TS_END_EC_SYNC = 518, - TS_START_COPYVPD = 550, - TS_END_COPYVPD_RO = 551, - TS_END_COPYVPD_RW = 552, - TS_START_TPM_ENABLE_UPDATE = 553, - TS_END_TPM_ENABLE_UPDATE = 554, + TS_EC_SYNC_END = 518, + TS_COPYVPD_START = 550, + TS_COPYVPD_RO_END = 551, + TS_COPYVPD_RW_END = 552, + TS_TPM_ENABLE_UPDATE_START = 553, + TS_TPM_ENABLE_UPDATE_END = 554, /* 900-940 reserved for vendorcode extensions (900-940: AMD) */ TS_AGESA_INIT_RESET_START = 900, - TS_AGESA_INIT_RESET_DONE = 901, + TS_AGESA_INIT_RESET_END = 901, TS_AGESA_INIT_EARLY_START = 902, - TS_AGESA_INIT_EARLY_DONE = 903, + TS_AGESA_INIT_EARLY_END = 903, TS_AGESA_INIT_POST_START = 904, - TS_AGESA_INIT_POST_DONE = 905, + TS_AGESA_INIT_POST_END = 905, TS_AGESA_INIT_ENV_START = 906, - TS_AGESA_INIT_ENV_DONE = 907, + TS_AGESA_INIT_ENV_END = 907, TS_AGESA_INIT_MID_START = 908, - TS_AGESA_INIT_MID_DONE = 909, + TS_AGESA_INIT_MID_END = 909, TS_AGESA_INIT_LATE_START = 910, - TS_AGESA_INIT_LATE_DONE = 911, + TS_AGESA_INIT_LATE_END = 911, TS_AGESA_INIT_RTB_START = 912, - TS_AGESA_INIT_RTB_DONE = 913, + TS_AGESA_INIT_RTB_END = 913, TS_AGESA_INIT_RESUME_START = 914, - TS_AGESA_INIT_RESUME_DONE = 915, + TS_AGESA_INIT_RESUME_END = 915, TS_AGESA_S3_LATE_START = 916, - TS_AGESA_S3_LATE_DONE = 917, + TS_AGESA_S3_LATE_END = 917, TS_AGESA_S3_FINAL_START = 918, - TS_AGESA_S3_FINAL_DONE = 919, + TS_AGESA_S3_FINAL_END = 919, TS_AMD_APOB_READ_START = 920, TS_AMD_APOB_ERASE_START = 921, TS_AMD_APOB_WRITE_START = 922, - TS_AMD_APOB_DONE = 923, + TS_AMD_APOB_END = 923, /* 940-950 reserved for vendorcode extensions (940-950: Intel ME) */ - TS_ME_INFORM_DRAM_WAIT = 940, - TS_ME_INFORM_DRAM_DONE = 941, - TS_ME_BEFORE_END_OF_POST = 942, - TS_ME_AFTER_END_OF_POST = 943, - TS_ME_BOOT_STALL_DONE = 944, + TS_ME_INFORM_DRAM_START = 940, + TS_ME_INFORM_DRAM_END = 941, + TS_ME_END_OF_POST_START = 942, + TS_ME_END_OF_POST_END = 943, + TS_ME_BOOT_STALL_END = 944, TS_ME_ICC_CONFIG_START = 945, - TS_ME_HOST_BOOT_PREP_DONE = 946, + TS_ME_HOST_BOOT_PREP_END = 946, TS_ME_RECEIVED_CRDA_FROM_PMC = 947, - TS_START_CSE_FW_SYNC = 948, - TS_END_CSE_FW_SYNC = 949, + TS_CSE_FW_SYNC_START = 948, + TS_CSE_FW_SYNC_END = 949, /* 950+ reserved for vendorcode extensions (950-989: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, @@ -129,12 +129,12 @@ TS_FSP_TEMP_RAM_EXIT_END = 953, TS_FSP_SILICON_INIT_START = 954, TS_FSP_SILICON_INIT_END = 955, - TS_FSP_BEFORE_ENUMERATE = 956, - TS_FSP_AFTER_ENUMERATE = 957, - TS_FSP_BEFORE_FINALIZE = 958, - TS_FSP_AFTER_FINALIZE = 959, - TS_FSP_BEFORE_END_OF_FIRMWARE = 960, - TS_FSP_AFTER_END_OF_FIRMWARE = 961, + TS_FSP_ENUMERATE_START = 956, + TS_FSP_ENUMERATE_END = 957, + TS_FSP_FINALIZE_START = 958, + TS_FSP_FINALIZE_END = 959, + TS_FSP_END_OF_FIRMWARE_START = 960, + TS_FSP_END_OF_FIRMWARE_END = 961, TS_FSP_MULTI_PHASE_SI_INIT_START = 962, TS_FSP_MULTI_PHASE_SI_INIT_END = 963, TS_FSP_MEMORY_INIT_LOAD = 970, @@ -161,7 +161,7 @@ TS_VB_READ_KERNEL_DONE = 1050, TS_VB_VBOOT_DONE = 1100, - TS_START_KERNEL = 1101, + TS_KERNEL_START = 1101, TS_KERNEL_DECOMPRESSION = 1102, }; @@ -171,23 +171,23 @@ } timestamp_ids[] = { /* Marker to report base_time. */ { 0, "1st timestamp" }, - { TS_START_ROMSTAGE, "start of romstage" }, - { TS_BEFORE_INITRAM, "before RAM initialization" }, - { TS_AFTER_INITRAM, "after RAM initialization" }, - { TS_END_ROMSTAGE, "end of romstage" }, - { TS_START_VBOOT, "start of verified boot" }, - { TS_END_VBOOT, "end of verified boot" }, - { TS_START_COPYRAM, "starting to load ramstage" }, - { TS_END_COPYRAM, "finished loading ramstage" }, - { TS_START_RAMSTAGE, "start of ramstage" }, - { TS_START_BOOTBLOCK, "start of bootblock" }, - { TS_END_BOOTBLOCK, "end of bootblock" }, - { TS_START_COPYROM, "starting to load romstage" }, - { TS_END_COPYROM, "finished loading romstage" }, - { TS_START_ULZMA, "starting LZMA decompress (ignore for x86)" }, - { TS_END_ULZMA, "finished LZMA decompress (ignore for x86)" }, - { TS_START_ULZ4F, "starting LZ4 decompress (ignore for x86)" }, - { TS_END_ULZ4F, "finished LZ4 decompress (ignore for x86)" }, + { TS_ROMSTAGE_START, "start of romstage" }, + { TS_INITRAM_START, "before RAM initialization" }, + { TS_INITRAM_END, "after RAM initialization" }, + { TS_ROMSTAGE_END, "end of romstage" }, + { TS_VBOOT_START, "start of verified boot" }, + { TS_VBOOT_END, "end of verified boot" }, + { TS_COPYRAM_START, "starting to load ramstage" }, + { TS_COPYRAM_END, "finished loading ramstage" }, + { TS_RAMSTAGE_START, "start of ramstage" }, + { TS_BOOTBLOCK_START, "start of bootblock" }, + { TS_BOOTBLOCK_END, "end of bootblock" }, + { TS_COPYROM_START, "starting to load romstage" }, + { TS_COPYROM_END, "finished loading romstage" }, + { TS_ULZMA_START, "starting LZMA decompress (ignore for x86)" }, + { TS_ULZMA_END, "finished LZMA decompress (ignore for x86)" }, + { TS_ULZ4F_START, "starting LZ4 decompress (ignore for x86)" }, + { TS_ULZ4F_END, "finished LZ4 decompress (ignore for x86)" }, { TS_DEVICE_ENUMERATE, "device enumeration" }, { TS_DEVICE_CONFIGURE, "device configuration" }, { TS_DEVICE_ENABLE, "device enable" }, @@ -209,31 +209,31 @@ { TS_ELOG_INIT_START, "started elog init" }, { TS_ELOG_INIT_END, "finished elog init" }, - { TS_START_COPYVER, "starting to load verstage" }, - { TS_END_COPYVER, "finished loading verstage" }, - { TS_START_TPMINIT, "starting to initialize TPM" }, - { TS_END_TPMINIT, "finished TPM initialization" }, - { TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" }, - { TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" }, - { TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " }, - { TS_DONE_LOADING, "finished loading body" }, - { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, - { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, - { TS_START_TPMPCR, "starting TPM PCR extend" }, - { TS_END_TPMPCR, "finished TPM PCR extend" }, - { TS_START_TPMLOCK, "starting locking TPM" }, - { TS_END_TPMLOCK, "finished locking TPM" }, - { TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" }, - { TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" }, + { TS_COPYVER_START, "starting to load verstage" }, + { TS_COPYVER_END, "finished loading verstage" }, + { TS_TPMINIT_START, "starting to initialize TPM" }, + { TS_TPMINIT_END, "finished TPM initialization" }, + { TS_VERIFY_SLOT_START, "starting to verify keyblock/preamble (RSA)" }, + { TS_VERIFY_SLOT_END, "finished verifying keyblock/preamble (RSA)" }, + { TS_HASH_BODY_START, "starting to verify body (load+SHA2+RSA) " }, + { TS_LOADING_END, "finished loading body" }, + { TS_HASHING_END, "finished calculating body hash (SHA2)" }, + { TS_HASH_BODY_END, "finished verifying body signature (RSA)" }, + { TS_TPMPCR_START, "starting TPM PCR extend" }, + { TS_TPMPCR_END, "finished TPM PCR extend" }, + { TS_TPMLOCK_START, "starting locking TPM" }, + { TS_TPMLOCK_END, "finished locking TPM" }, + { TS_TPM_ENABLE_UPDATE_START, "started TPM enable update" }, + { TS_TPM_ENABLE_UPDATE_END, "finished TPM enable update" }, - { TS_START_COPYVPD, "starting to load Chrome OS VPD" }, - { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, - { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" }, + { TS_COPYVPD_START, "starting to load Chrome OS VPD" }, + { TS_COPYVPD_RO_END, "finished loading Chrome OS VPD (RO)" }, + { TS_COPYVPD_RW_END, "finished loading Chrome OS VPD (RW)" }, - { TS_START_EC_SYNC, "starting EC software sync" }, + { TS_EC_SYNC_START, "starting EC software sync" }, { TS_EC_HASH_READY, "EC vboot hash ready" }, { TS_EC_POWER_LIMIT_WAIT, "waiting for EC to allow higher power draw" }, - { TS_END_EC_SYNC, "finished EC software sync" }, + { TS_EC_SYNC_END, "finished EC software sync" }, { TS_DC_START, "depthcharge start" }, { TS_RO_PARAMS_INIT, "RO parameter init" }, @@ -247,45 +247,45 @@ { TS_VB_READ_KERNEL_DONE, "finished reading kernel from disk" }, { TS_VB_VBOOT_DONE, "finished vboot kernel verification" }, { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, - { TS_START_KERNEL, "jumping to kernel" }, + { TS_KERNEL_START, "jumping to kernel" }, /* AMD related timestamps */ { TS_AGESA_INIT_RESET_START, "calling AmdInitReset" }, - { TS_AGESA_INIT_RESET_DONE, "back from AmdInitReset" }, + { TS_AGESA_INIT_RESET_END, "back from AmdInitReset" }, { TS_AGESA_INIT_EARLY_START, "calling AmdInitEarly" }, - { TS_AGESA_INIT_EARLY_DONE, "back from AmdInitEarly" }, + { TS_AGESA_INIT_EARLY_END, "back from AmdInitEarly" }, { TS_AGESA_INIT_POST_START, "calling AmdInitPost" }, - { TS_AGESA_INIT_POST_DONE, "back from AmdInitPost" }, + { TS_AGESA_INIT_POST_END, "back from AmdInitPost" }, { TS_AGESA_INIT_ENV_START, "calling AmdInitEnv" }, - { TS_AGESA_INIT_ENV_DONE, "back from AmdInitEnv" }, + { TS_AGESA_INIT_ENV_END, "back from AmdInitEnv" }, { TS_AGESA_INIT_MID_START, "calling AmdInitMid" }, - { TS_AGESA_INIT_MID_DONE, "back from AmdInitMid" }, + { TS_AGESA_INIT_MID_END, "back from AmdInitMid" }, { TS_AGESA_INIT_LATE_START, "calling AmdInitLate" }, - { TS_AGESA_INIT_LATE_DONE, "back from AmdInitLate" }, + { TS_AGESA_INIT_LATE_END, "back from AmdInitLate" }, { TS_AGESA_INIT_RTB_START, "calling AmdInitRtb/AmdS3Save" }, - { TS_AGESA_INIT_RTB_DONE, "back from AmdInitRtb/AmdS3Save" }, + { TS_AGESA_INIT_RTB_END, "back from AmdInitRtb/AmdS3Save" }, { TS_AGESA_INIT_RESUME_START, "calling AmdInitResume" }, - { TS_AGESA_INIT_RESUME_DONE, "back from AmdInitResume" }, + { TS_AGESA_INIT_RESUME_END, "back from AmdInitResume" }, { TS_AGESA_S3_LATE_START, "calling AmdS3LateRestore" }, - { TS_AGESA_S3_LATE_DONE, "back from AmdS3LateRestore" }, + { TS_AGESA_S3_LATE_END, "back from AmdS3LateRestore" }, { TS_AGESA_S3_FINAL_START, "calling AmdS3FinalRestore" }, - { TS_AGESA_S3_FINAL_DONE, "back from AmdS3FinalRestore" }, + { TS_AGESA_S3_FINAL_END, "back from AmdS3FinalRestore" }, { TS_AMD_APOB_READ_START, "starting APOB read" }, { TS_AMD_APOB_ERASE_START, "starting APOB erase" }, { TS_AMD_APOB_WRITE_START, "starting APOB write" }, - { TS_AMD_APOB_DONE, "finished APOB" }, + { TS_AMD_APOB_END, "finished APOB" }, /* Intel ME related timestamps */ - { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, - { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, - { TS_ME_BEFORE_END_OF_POST, "before sending EOP to ME"}, - { TS_ME_AFTER_END_OF_POST, "after sending EOP to ME"}, - { TS_ME_BOOT_STALL_DONE, "CSE sent 'Boot Stall Done' to PMC"}, + { TS_ME_INFORM_DRAM_START, "waiting for ME acknowledgement of raminit"}, + { TS_ME_INFORM_DRAM_END, "finished waiting for ME response"}, + { TS_ME_END_OF_POST_START, "before sending EOP to ME"}, + { TS_ME_END_OF_POST_END, "after sending EOP to ME"}, + { TS_ME_BOOT_STALL_END, "CSE sent 'Boot Stall Done' to PMC"}, { TS_ME_ICC_CONFIG_START, "CSE started to handle ICC configuration"}, - { TS_ME_HOST_BOOT_PREP_DONE, "CSE sent 'Host BIOS Prep Done' to PMC"}, + { TS_ME_HOST_BOOT_PREP_END, "CSE sent 'Host BIOS Prep Done' to PMC"}, { TS_ME_RECEIVED_CRDA_FROM_PMC, "CSE received 'CPU Reset Done Ack sent' from PMC"}, - { TS_START_CSE_FW_SYNC, "starting CSE firmware sync"}, - { TS_END_CSE_FW_SYNC, "finished CSE firmware sync"}, + { TS_CSE_FW_SYNC_START, "starting CSE firmware sync"}, + { TS_CSE_FW_SYNC_END, "finished CSE firmware sync"}, { TS_ME_ROM_START, "CSME ROM started execution"}, /* FSP related timestamps */ @@ -297,20 +297,20 @@ { TS_FSP_SILICON_INIT_END, "returning from FspSiliconInit" }, { TS_FSP_MULTI_PHASE_SI_INIT_START, "calling FspMultiPhaseSiInit" }, { TS_FSP_MULTI_PHASE_SI_INIT_END, "returning from FspMultiPhaseSiInit" }, - { TS_FSP_BEFORE_ENUMERATE, "calling FspNotify(AfterPciEnumeration)" }, - { TS_FSP_AFTER_ENUMERATE, + { TS_FSP_ENUMERATE_START, "calling FspNotify(AfterPciEnumeration)" }, + { TS_FSP_ENUMERATE_END, "returning from FspNotify(AfterPciEnumeration)" }, - { TS_FSP_BEFORE_FINALIZE, "calling FspNotify(ReadyToBoot)" }, - { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" }, - { TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" }, - { TS_FSP_AFTER_END_OF_FIRMWARE, + { TS_FSP_FINALIZE_START, "calling FspNotify(ReadyToBoot)" }, + { TS_FSP_FINALIZE_END, "returning from FspNotify(ReadyToBoot)" }, + { TS_FSP_END_OF_FIRMWARE_START, "calling FspNotify(EndOfFirmware)" }, + { TS_FSP_END_OF_FIRMWARE_END, "returning from FspNotify(EndOfFirmware)" }, { TS_FSP_MEMORY_INIT_LOAD, "loading FSP-M" }, { TS_FSP_SILICON_INIT_LOAD, "loading FSP-S" }, - { TS_START_POSTCAR, "start of postcar" }, - { TS_END_POSTCAR, "end of postcar" }, + { TS_POSTCAR_START, "start of postcar" }, + { TS_POSTCAR_END, "end of postcar" }, }; #endif diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 63ddd74..85bc894 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -60,7 +60,7 @@ asmlinkage void car_stage_entry(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); /* Assumes the hardware was set up during the bootblock */ console_init(); diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 126a2ee..7154c95 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -28,69 +28,69 @@ .func = AMD_INIT_RESET, .name = "AmdInitReset", .entry_id = TS_AGESA_INIT_RESET_START, - .exit_id = TS_AGESA_INIT_RESET_DONE, + .exit_id = TS_AGESA_INIT_RESET_END, }, { .func = AMD_INIT_EARLY, .name = "AmdInitEarly", .entry_id = TS_AGESA_INIT_EARLY_START, - .exit_id = TS_AGESA_INIT_EARLY_DONE, + .exit_id = TS_AGESA_INIT_EARLY_END, }, { .func = AMD_INIT_POST, .name = "AmdInitPost", .entry_id = TS_AGESA_INIT_POST_START, - .exit_id = TS_AGESA_INIT_POST_DONE, + .exit_id = TS_AGESA_INIT_POST_END, }, { .func = AMD_INIT_RESUME, .name = "AmdInitResume", .entry_id = TS_AGESA_INIT_RESUME_START, - .exit_id = TS_AGESA_INIT_RESUME_DONE, + .exit_id = TS_AGESA_INIT_RESUME_END, }, { .func = AMD_INIT_ENV, .name = "AmdInitEnv", .entry_id = TS_AGESA_INIT_ENV_START, - .exit_id = TS_AGESA_INIT_ENV_DONE, + .exit_id = TS_AGESA_INIT_ENV_END, }, { .func = AMD_INIT_MID, .name = "AmdInitMid", .entry_id = TS_AGESA_INIT_MID_START, - .exit_id = TS_AGESA_INIT_MID_DONE, + .exit_id = TS_AGESA_INIT_MID_END, }, { .func = AMD_INIT_LATE, .name = "AmdInitLate", .entry_id = TS_AGESA_INIT_LATE_START, - .exit_id = TS_AGESA_INIT_LATE_DONE, + .exit_id = TS_AGESA_INIT_LATE_END, }, { .func = AMD_S3LATE_RESTORE, .name = "AmdS3LateRestore", .entry_id = TS_AGESA_S3_LATE_START, - .exit_id = TS_AGESA_S3_LATE_DONE, + .exit_id = TS_AGESA_S3_LATE_END, }, #if !defined(AMD_S3_SAVE_REMOVED) { .func = AMD_S3_SAVE, .name = "AmdS3Save", .entry_id = TS_AGESA_INIT_RTB_START, - .exit_id = TS_AGESA_INIT_RTB_DONE, + .exit_id = TS_AGESA_INIT_RTB_END, }, #endif { .func = AMD_S3FINAL_RESTORE, .name = "AmdS3FinalRestore", .entry_id = TS_AGESA_S3_FINAL_START, - .exit_id = TS_AGESA_S3_FINAL_DONE, + .exit_id = TS_AGESA_S3_FINAL_END, }, { .func = AMD_INIT_RTB, .name = "AmdInitRtb", .entry_id = TS_AGESA_INIT_RTB_START, - .exit_id = TS_AGESA_INIT_RTB_DONE, + .exit_id = TS_AGESA_INIT_RTB_END, }, }; diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 871054b..5968f73 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -40,7 +40,7 @@ fill_sysinfo(cb); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); board_BeforeAgesa(cb); @@ -55,14 +55,14 @@ agesa_execute_state(cb, AMD_INIT_EARLY); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); if (!cb->s3resume) agesa_execute_state(cb, AMD_INIT_POST); else agesa_execute_state(cb, AMD_INIT_RESUME); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Work around AGESA setting all memory as WB on normal * boot path. diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 570648c..7dc16c3 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -134,17 +134,17 @@ notify_phase_params.Phase = phase; if (phase == EnumInitPhaseReadyToBoot) { - timestamp_add_now(TS_FSP_BEFORE_FINALIZE); + timestamp_add_now(TS_FSP_FINALIZE_START); post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); } else { - timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); + timestamp_add_now(TS_FSP_ENUMERATE_START); post_code(POST_FSP_NOTIFY_BEFORE_ENUMERATE); } status = notify_phase_proc(&notify_phase_params); timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? - TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); + TS_FSP_FINALIZE_END : TS_FSP_ENUMERATE_END); if (status != 0) printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 3ed73d3..7fd1cf5 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -26,7 +26,7 @@ post_code(0x32); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); s3wake = params->power_state->prev_sleep_state == ACPI_S3; @@ -66,7 +66,7 @@ /* Initialize RAM */ raminit(params); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Save MRC output */ if (CONFIG(CACHE_MRC_SETTINGS)) { @@ -100,7 +100,7 @@ post_code(0x30); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); /* Display parameters */ if (!CONFIG(NO_ECAM_MMCONF_SUPPORT)) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b7e81f0..1612089 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -380,9 +380,9 @@ die("FSPM XIP base does not match: %p vs %p\n", (void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog)); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); do_fsp_memory_init(&context, s3wake); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 30d61c9..5cd63d8 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -23,24 +23,24 @@ .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM), .post_code_before = POST_FSP_NOTIFY_BEFORE_ENUMERATE, .post_code_after = POST_FSP_NOTIFY_AFTER_ENUMERATE, - .timestamp_before = TS_FSP_BEFORE_ENUMERATE, - .timestamp_after = TS_FSP_AFTER_ENUMERATE, + .timestamp_before = TS_FSP_ENUMERATE_START, + .timestamp_after = TS_FSP_ENUMERATE_END, }, { .notify_phase = READY_TO_BOOT, .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT), .post_code_before = POST_FSP_NOTIFY_BEFORE_FINALIZE, .post_code_after = POST_FSP_NOTIFY_AFTER_FINALIZE, - .timestamp_before = TS_FSP_BEFORE_FINALIZE, - .timestamp_after = TS_FSP_AFTER_FINALIZE, + .timestamp_before = TS_FSP_FINALIZE_START, + .timestamp_after = TS_FSP_FINALIZE_END, }, { .notify_phase = END_OF_FIRMWARE, .skip = !CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE), .post_code_before = POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE, .post_code_after = POST_FSP_NOTIFY_AFTER_END_OF_FIRMWARE, - .timestamp_before = TS_FSP_BEFORE_END_OF_FIRMWARE, - .timestamp_after = TS_FSP_AFTER_END_OF_FIRMWARE, + .timestamp_before = TS_FSP_END_OF_FIRMWARE_START, + .timestamp_after = TS_FSP_END_OF_FIRMWARE_END, }, }; diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index 396097c..32ec0a0 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -126,7 +126,7 @@ { struct vpd_cbmem *cbmem; - timestamp_add_now(TS_START_COPYVPD); + timestamp_add_now(TS_COPYVPD_START); init_vpd_rdevs(); @@ -154,7 +154,7 @@ printk(BIOS_ERR, "Couldn't read RO VPD\n"); cbmem->ro_size = ro_size = 0; } - timestamp_add_now(TS_END_COPYVPD_RO); + timestamp_add_now(TS_COPYVPD_RO_END); } if (rw_size) { @@ -163,7 +163,7 @@ printk(BIOS_ERR, "Couldn't read RW VPD\n"); cbmem->rw_size = rw_size = 0; } - timestamp_add_now(TS_END_COPYVPD_RW); + timestamp_add_now(TS_COPYVPD_RW_END); } init_vpd_rdevs_from_cbmem(); diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 5989964..5c202ba 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -39,7 +39,7 @@ timestamps[i].entry_stamp); } - timestamp_add_now(TS_START_BOOTBLOCK); + timestamp_add_now(TS_BOOTBLOCK_START); bootblock_soc_early_init(); bootblock_mainboard_early_init(); @@ -63,7 +63,7 @@ tpm_setup(s3resume); } - timestamp_add_now(TS_END_BOOTBLOCK); + timestamp_add_now(TS_BOOTBLOCK_END); run_romstage(); } diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 2d98c44..0f07a32 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -215,9 +215,9 @@ return 0; if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) { - timestamp_add_now(TS_START_ULZ4F); + timestamp_add_now(TS_ULZ4F_START); out_size = ulz4fn(map, in_size, buffer, buffer_size); - timestamp_add_now(TS_END_ULZ4F); + timestamp_add_now(TS_ULZ4F_END); } rdev_munmap(rdev, map); @@ -233,9 +233,9 @@ if (!cbfs_file_hash_mismatch(map, in_size, mdata, skip_verification)) { /* Note: timestamp not useful for memory-mapped media (x86) */ - timestamp_add_now(TS_START_ULZMA); + timestamp_add_now(TS_ULZMA_START); out_size = ulzman(map, in_size, buffer, buffer_size); - timestamp_add_now(TS_END_ULZMA); + timestamp_add_now(TS_ULZMA_END); } rdev_munmap(rdev, map); diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 1d160e0..22d31df 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -23,8 +23,8 @@ .base_timestamp = 0, .num_timestamps = 2, .timestamps = { - { .entry_id = TS_START_ULZ4F }, - { .entry_id = TS_END_ULZ4F }, + { .entry_id = TS_ULZ4F_START }, + { .entry_id = TS_ULZ4F_END }, }, }; diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index d61bfd5..21bc4e8 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -62,14 +62,14 @@ true_size = node->size; break; case CBFS_COMPRESS_LZMA: - timestamp_add_now(TS_START_ULZMA); + timestamp_add_now(TS_ULZMA_START); true_size = ulzman(node->data, node->size, dst, region->size); - timestamp_add_now(TS_END_ULZMA); + timestamp_add_now(TS_ULZMA_END); break; case CBFS_COMPRESS_LZ4: - timestamp_add_now(TS_START_ULZ4F); + timestamp_add_now(TS_ULZ4F_START); true_size = ulz4fn(node->data, node->size, dst, region->size); - timestamp_add_now(TS_END_ULZ4F); + timestamp_add_now(TS_ULZ4F_END); break; default: return true; @@ -240,5 +240,5 @@ return; } - timestamp_add_now(TS_START_KERNEL); + timestamp_add_now(TS_KERNEL_START); } diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index b646e0c..b5ed6e0 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -457,7 +457,7 @@ */ cbmem_initialize(); - timestamp_add_now(TS_START_RAMSTAGE); + timestamp_add_now(TS_RAMSTAGE_START); post_code(POST_ENTRY_HARDWAREMAIN); /* Handoff sleep type from romstage. */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 25a8836..a296bd6 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -24,7 +24,7 @@ vboot_run_logic(); - timestamp_add_now(TS_START_COPYROM); + timestamp_add_now(TS_COPYROM_START); if (ENV_X86 && CONFIG(BOOTBLOCK_NORMAL)) { if (legacy_romstage_select_and_load(&romstage)) @@ -34,7 +34,7 @@ goto fail; } - timestamp_add_now(TS_END_COPYROM); + timestamp_add_now(TS_COPYROM_END); console_time_report(); @@ -90,11 +90,11 @@ PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage"); if (ENV_POSTCAR) - timestamp_add_now(TS_END_POSTCAR); + timestamp_add_now(TS_POSTCAR_END); /* Call "end of romstage" here if postcar stage doesn't exist */ if (ENV_ROMSTAGE) - timestamp_add_now(TS_END_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_END); /* * Only x86 systems using ramstage stage cache currently take the same @@ -105,7 +105,7 @@ vboot_run_logic(); - timestamp_add_now(TS_START_COPYRAM); + timestamp_add_now(TS_COPYRAM_START); if (ENV_X86) { if (load_relocatable_ramstage(&ramstage)) @@ -117,7 +117,7 @@ stage_cache_add(STAGE_RAMSTAGE, &ramstage); - timestamp_add_now(TS_END_COPYRAM); + timestamp_add_now(TS_COPYRAM_END); console_time_report(); diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index f1c0b97..70ab719 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -72,18 +72,18 @@ switch (compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - timestamp_add_now(TS_START_ULZMA); + timestamp_add_now(TS_ULZMA_START); len = ulzman(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZMA); + timestamp_add_now(TS_ULZMA_END); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_LZ4: { printk(BIOS_DEBUG, "using LZ4\n"); - timestamp_add_now(TS_START_ULZ4F); + timestamp_add_now(TS_ULZ4F_START); len = ulz4fn(src, len, dest, memsz); - timestamp_add_now(TS_END_ULZ4F); + timestamp_add_now(TS_ULZ4F_END); if (!len) /* Decompression Error. */ return 0; break; diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index b8105fd..dd3bc72 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -123,7 +123,7 @@ int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ @@ -134,11 +134,11 @@ setup_power(is_resume); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); setup_memory(mem, is_resume); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* This needs to happen on normal boots and on resume. */ trustzone_init(); diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 9579047..4ae7ef0 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -24,7 +24,7 @@ static void __attribute__((noinline)) romstage(void) { timestamp_init(0); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 9579047..4ae7ef0 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -24,7 +24,7 @@ static void __attribute__((noinline)) romstage(void) { timestamp_init(0); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index f1087d0..229e236 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -25,7 +25,7 @@ static void __attribute__((noinline)) romstage(void) { timestamp_init(0); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 83d38fa..3509a45 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -212,7 +212,7 @@ power_init_failed = setup_power(is_resume); timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ @@ -228,11 +228,11 @@ /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); setup_memory(&mem_timings, is_resume); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); primitive_mem_test(); diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 35ddf85..de4617c 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -64,7 +64,7 @@ void main(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); @@ -77,11 +77,11 @@ /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_init(get_sdram_config()); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index bac2acb..fb0230a 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -58,7 +58,7 @@ void main(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); @@ -68,11 +68,11 @@ /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_init(get_sdram_config()); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index acea7a0..db2e343 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -64,7 +64,7 @@ void main(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); console_init(); exception_init(); @@ -77,11 +77,11 @@ /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_init(get_sdram_config()); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 4a8cf90..22a14ae 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1704,7 +1704,7 @@ if (!e7505_mch_is_ready()) { /* The real MCH initialisation. */ - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); @@ -1713,7 +1713,7 @@ /* Hook for post ECC scrub settings and debug. */ sdram_post_ecc(memctrl); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); } printk(BIOS_DEBUG, "SDRAM is up.\n"); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 6e505da..35d71c0 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1695,7 +1695,7 @@ int ch; - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); /* Wait for some bit, maybe TXT clear. */ if (sysinfo->txt_enabled) { @@ -1803,5 +1803,5 @@ raminit_thermal(sysinfo); init_igd(sysinfo); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); } diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index e1a9337..5336769 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -405,13 +405,13 @@ pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); copy_spd(&pei_data, &spdi); sdram_initialize(&pei_data); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); post_code(0x3b); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index e5d377e..93cbeb9 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1004,7 +1004,7 @@ void sdram_initialize(int s3resume) { - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); enable_spd(); dump_spd_registers(); @@ -1013,5 +1013,5 @@ sdram_enable(); disable_spd(); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); } diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e168f7c..982099e 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2683,7 +2683,7 @@ { struct sys_info sysinfo; - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); memset(&sysinfo, 0, sizeof(sysinfo)); @@ -2783,5 +2783,5 @@ printk(BIOS_DEBUG, "RAM initialization finished.\n"); sdram_setup_processor_side(); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); } diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 242100b..f717782 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -42,7 +42,7 @@ early_thermal_init(); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); chipset_init(s3resume); @@ -52,7 +52,7 @@ raminit(s3resume, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); intel_early_me_status(); diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index a98ae99..03058ec 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -50,9 +50,9 @@ get_mb_spd_addrmap(&spd_addrmap[0]); printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a3e7016..9082f8a 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -298,7 +298,7 @@ size_t mrc_size; ramctr_timing *ctrl_cached = NULL; - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); mchbar_setbits32(SAPMCTL, 1 << 0); @@ -460,7 +460,7 @@ report_memory_config(); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); cbmem_was_inited = !cbmem_recovery(s3resume); if (!fast_boot) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c52203a..fbb2b6e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -364,9 +364,9 @@ disable_p2p(); pei_data.boot_mode = s3resume ? 2 : 0; - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); sdram_initialize(&pei_data); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 460916b..2f844a5 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -566,7 +566,7 @@ int fast_boot, cbmem_was_inited; size_t mrc_size; - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); printk(BIOS_DEBUG, "Setting up RAM controller.\n"); pci_write_config8(HOST_BRIDGE, 0xdf, 0xff); @@ -638,7 +638,7 @@ pci_or_config8(HOST_BRIDGE, 0xf4, 1); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); printk(BIOS_DEBUG, "RAM initialization finished.\n"); diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index f31b783..56e6c44 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -42,7 +42,7 @@ vb2_error_t retval = VB2_SUCCESS; struct vb2_context *ctx; - timestamp_add_now(TS_START_EC_SYNC); + timestamp_add_now(TS_EC_SYNC_START); ctx = vboot_get_context(); ctx->flags |= VB2_CONTEXT_EC_SYNC_SUPPORTED; @@ -84,7 +84,7 @@ break; } - timestamp_add_now(TS_END_EC_SYNC); + timestamp_add_now(TS_EC_SYNC_END); } /* Convert firmware image type into a flash offset */ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 482c6fb..1c4343b 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -52,10 +52,10 @@ printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n"); - timestamp_add_now(TS_START_COPYVER); + timestamp_add_now(TS_COPYVER_START); if (cbfs_prog_stage_load(&verstage)) die("failed to load verstage"); - timestamp_add_now(TS_END_COPYVER); + timestamp_add_now(TS_COPYVER_END); /* verify and select a slot */ prog_run(&verstage); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 91d42b2..509169f 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -140,7 +140,7 @@ * (This split won't make sense with memory-mapped media like on x86.) */ load_ts = timestamp_get(); - timestamp_add(TS_START_HASH_BODY, load_ts); + timestamp_add(TS_HASH_BODY_START, load_ts); remaining = region_device_sz(fw_body); offset = 0; @@ -169,15 +169,15 @@ offset += block_size; } - timestamp_add(TS_DONE_LOADING, load_ts); - timestamp_add_now(TS_DONE_HASHING); + timestamp_add(TS_LOADING_END, load_ts); + timestamp_add_now(TS_HASHING_END); /* Check the result (with RSA signature verification) */ rv = vb2api_check_hash_get_digest(ctx, hash_digest, hash_digest_sz); if (rv) return rv; - timestamp_add_now(TS_END_HASH_BODY); + timestamp_add_now(TS_HASH_BODY_END); if (handle_digest_result(hash_digest, hash_digest_sz)) return VB2_ERROR_UNKNOWN; @@ -248,7 +248,7 @@ struct region_device fw_body; vb2_error_t rv; - timestamp_add_now(TS_START_VBOOT); + timestamp_add_now(TS_VBOOT_START); /* Lockdown SPI flash controller if required */ if (CONFIG(BOOTMEDIA_LOCK_IN_VERSTAGE)) @@ -271,12 +271,12 @@ /* Read secdata from TPM. Initialize TPM if secdata not found. We don't * check the return value here because vb2api_fw_phase1 will catch * invalid secdata and tell us what to do (=reboot). */ - timestamp_add_now(TS_START_TPMINIT); + timestamp_add_now(TS_TPMINIT_START); if (vboot_setup_tpm(ctx) == TPM_SUCCESS) { antirollback_read_space_firmware(ctx); antirollback_read_space_kernel(ctx); } - timestamp_add_now(TS_END_TPMINIT); + timestamp_add_now(TS_TPMINIT_END); if (get_recovery_mode_switch()) { ctx->flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; @@ -343,9 +343,9 @@ /* Try that slot (verify its keyblock and preamble) */ printk(BIOS_INFO, "Phase 3\n"); - timestamp_add_now(TS_START_VERIFY_SLOT); + timestamp_add_now(TS_VERIFY_SLOT_START); rv = vb2api_fw_phase3(ctx); - timestamp_add_now(TS_END_VERIFY_SLOT); + timestamp_add_now(TS_VERIFY_SLOT_END); if (rv) { printk(BIOS_INFO, "Reboot requested (%x)\n", rv); vboot_save_data(ctx); @@ -367,7 +367,7 @@ /* Only extend PCRs once on boot. */ if (!(ctx->flags & VB2_CONTEXT_S3_RESUME)) { - timestamp_add_now(TS_START_TPMPCR); + timestamp_add_now(TS_TPMPCR_START); rv = extend_pcrs(ctx); if (rv) { printk(BIOS_WARNING, @@ -376,12 +376,12 @@ vboot_save_data(ctx); vboot_reboot(); } - timestamp_add_now(TS_END_TPMPCR); + timestamp_add_now(TS_TPMPCR_END); } /* Lock TPM */ - timestamp_add_now(TS_START_TPMLOCK); + timestamp_add_now(TS_TPMLOCK_START); rv = antirollback_lock_space_firmware(); if (rv) { printk(BIOS_INFO, "Failed to lock TPM (%x)\n", rv); @@ -389,7 +389,7 @@ vboot_save_data(ctx); vboot_reboot(); } - timestamp_add_now(TS_END_TPMLOCK); + timestamp_add_now(TS_TPMLOCK_END); /* Lock rec hash space if available. */ if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) { @@ -408,5 +408,5 @@ vboot_is_firmware_slot_a(ctx) ? 'A' : 'B'); verstage_main_exit: - timestamp_add_now(TS_END_VBOOT); + timestamp_add_now(TS_VBOOT_END); } diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index 9e863c3..9628571 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -12,7 +12,7 @@ asmlinkage void car_stage_entry(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); post_code(0x40); diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c index b932458..f203377 100644 --- a/src/soc/amd/common/block/apob/apob_cache.c +++ b/src/soc/amd/common/block/apob/apob_cache.c @@ -171,7 +171,7 @@ printk(BIOS_DEBUG, "APOB valid copy is already in flash\n"); if (!update_needed) { - timestamp_add_now(TS_AMD_APOB_DONE); + timestamp_add_now(TS_AMD_APOB_END); return; } @@ -199,7 +199,7 @@ return; } - timestamp_add_now(TS_AMD_APOB_DONE); + timestamp_add_now(TS_AMD_APOB_END); printk(BIOS_INFO, "Updated APOB in flash\n"); } diff --git a/src/soc/amd/common/pi/agesawrapper.c b/src/soc/amd/common/pi/agesawrapper.c index 8ee962b..c5e6cac 100644 --- a/src/soc/amd/common/pi/agesawrapper.c +++ b/src/soc/amd/common/pi/agesawrapper.c @@ -102,7 +102,7 @@ timestamp_add_now(TS_AGESA_INIT_RESET_START); status = amd_dispatch(ResetParams); - timestamp_add_now(TS_AGESA_INIT_RESET_DONE); + timestamp_add_now(TS_AGESA_INIT_RESET_END); return status; } @@ -116,7 +116,7 @@ timestamp_add_now(TS_AGESA_INIT_EARLY_START); status = amd_dispatch(EarlyParams); - timestamp_add_now(TS_AGESA_INIT_EARLY_DONE); + timestamp_add_now(TS_AGESA_INIT_EARLY_END); return status; } @@ -173,7 +173,7 @@ timestamp_add_now(TS_AGESA_INIT_POST_START); status = amd_dispatch(PostParams); - timestamp_add_now(TS_AGESA_INIT_POST_DONE); + timestamp_add_now(TS_AGESA_INIT_POST_END); /* * AGESA passes back the base and size of UMA. This is the only @@ -208,7 +208,7 @@ timestamp_add_now(TS_AGESA_INIT_ENV_START); status = amd_dispatch(EnvParams); - timestamp_add_now(TS_AGESA_INIT_ENV_DONE); + timestamp_add_now(TS_AGESA_INIT_ENV_END); return status; } @@ -251,7 +251,7 @@ timestamp_add_now(TS_AGESA_INIT_MID_START); status = amd_dispatch(MidParams); - timestamp_add_now(TS_AGESA_INIT_MID_DONE); + timestamp_add_now(TS_AGESA_INIT_MID_END); return status; } @@ -268,7 +268,7 @@ timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = amd_dispatch(LateParams); - timestamp_add_now(TS_AGESA_INIT_LATE_DONE); + timestamp_add_now(TS_AGESA_INIT_LATE_END); DmiTable = LateParams->DmiTable; AcpiPstate = LateParams->AcpiPState; @@ -295,7 +295,7 @@ timestamp_add_now(TS_AGESA_INIT_RTB_START); Status = amd_dispatch(RtbParams); - timestamp_add_now(TS_AGESA_INIT_RTB_DONE); + timestamp_add_now(TS_AGESA_INIT_RTB_END); if (Status != AGESA_SUCCESS) return Status; @@ -314,7 +314,7 @@ timestamp_add_now(TS_AGESA_INIT_RESUME_START); status = amd_dispatch(InitResumeParams); - timestamp_add_now(TS_AGESA_INIT_RESUME_DONE); + timestamp_add_now(TS_AGESA_INIT_RESUME_END); return status; } @@ -329,7 +329,7 @@ timestamp_add_now(TS_AGESA_S3_LATE_START); Status = amd_dispatch(S3LateParams); - timestamp_add_now(TS_AGESA_S3_LATE_DONE); + timestamp_add_now(TS_AGESA_S3_LATE_END); return Status; } @@ -342,7 +342,7 @@ timestamp_add_now(TS_AGESA_S3_FINAL_START); Status = amd_dispatch(S3FinalParams); - timestamp_add_now(TS_AGESA_S3_FINAL_DONE); + timestamp_add_now(TS_AGESA_S3_FINAL_END); return Status; } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 1972410..359eacf 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -13,7 +13,7 @@ asmlinkage void car_stage_entry(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); post_code(0x40); diff --git a/src/soc/amd/sabrina/romstage.c b/src/soc/amd/sabrina/romstage.c index 91f80ef..49ca223 100644 --- a/src/soc/amd/sabrina/romstage.c +++ b/src/soc/amd/sabrina/romstage.c @@ -14,7 +14,7 @@ asmlinkage void car_stage_entry(void) { - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); post_code(0x40); diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index ae83d49..9720d9e 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -137,9 +137,9 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { - timestamp_add_now(TS_START_CSE_FW_SYNC); + timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); - timestamp_add_now(TS_END_CSE_FW_SYNC); + timestamp_add_now(TS_CSE_FW_SYNC_END); } /* diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index dbf4afc..74238e2 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -101,7 +101,7 @@ memset(&mp, 0, sizeof(mp)); mainboard_fill_mrc_params(&mp); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); ps = fill_power_state(); prev_sleep_state = chipset_prev_sleep_state(ps); @@ -115,7 +115,7 @@ /* Initialize RAM */ raminit(&mp, prev_sleep_state); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 28b3f37..95073d3 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -188,14 +188,14 @@ post_code(0x32); - timestamp_add_now(TS_BEFORE_INITRAM); + timestamp_add_now(TS_INITRAM_START); pei_data.boot_mode = power_state->prev_sleep_state; /* Initialize RAM */ sdram_initialize(&pei_data); - timestamp_add_now(TS_AFTER_INITRAM); + timestamp_add_now(TS_INITRAM_END); int cbmem_was_initted = !cbmem_recovery(s3resume); if (s3resume && !cbmem_was_initted) { diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 3a08a73..af6abb8 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -192,9 +192,9 @@ set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); - timestamp_add_now(TS_ME_BEFORE_END_OF_POST); + timestamp_add_now(TS_ME_END_OF_POST_START); handle_cse_eop_result(cse_send_eop()); - timestamp_add_now(TS_ME_AFTER_END_OF_POST); + timestamp_add_now(TS_ME_END_OF_POST_END); set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 561bed9..866996f 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -166,7 +166,7 @@ "ME: ME is reporting as disabled, " "so not waiting for a response.\n"); } else { - timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); + timestamp_add_now(TS_ME_INFORM_DRAM_START); udelay(100); millisec = 0; do { @@ -177,7 +177,7 @@ millisec++; } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec <= 5000)); - timestamp_add_now(TS_ME_INFORM_DRAM_DONE); + timestamp_add_now(TS_ME_INFORM_DRAM_END); } me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES); diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index 0a24d0f..9ac33a5 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -89,7 +89,7 @@ return; } - timestamp_add_now(TS_START_TPM_ENABLE_UPDATE); + timestamp_add_now(TS_TPM_ENABLE_UPDATE_START); /* Reboot in 1000 ms if necessary. */ ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS, @@ -117,7 +117,7 @@ */ cr50_reset_reqd = cr50_is_reset_needed(); if (!cr50_reset_reqd) { - timestamp_add_now(TS_END_TPM_ENABLE_UPDATE); + timestamp_add_now(TS_TPM_ENABLE_UPDATE_END); return; } diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c index 06a5a00..a3f50db 100644 --- a/tests/lib/timestamp-test.c +++ b/tests/lib/timestamp-test.c @@ -25,7 +25,7 @@ timestamp_init(timestamp_base); - timestamp_add(TS_START_ROMSTAGE, base_multipler); + timestamp_add(TS_ROMSTAGE_START, base_multipler); assert_int_equal(1, glob_ts_table->num_entries); @@ -61,7 +61,7 @@ dummy_timestamp_set(base_multipler); - timestamp_add_now(TS_START_ROMSTAGE); + timestamp_add_now(TS_ROMSTAGE_START); assert_int_equal(1, glob_ts_table->num_entries); -- To view, visit https://review.coreboot.org/c/coreboot/+/62019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Gerrit-Change-Number: 62019 Gerrit-PatchSet: 9 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk IV
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58428 ) Change subject: mb/starlabs/labtop: Add LabTop Mk IV ...................................................................... mb/starlabs/labtop: Add LabTop Mk IV Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iv-specification Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58428 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop_cml.md M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/starlabs/labtop/Kconfig.name M src/mainboard/starlabs/labtop/Makefile.inc M src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/spd/Makefile.inc A src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex A src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex A src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex A src/mainboard/starlabs/labtop/variants/cml/Makefile.inc A src/mainboard/starlabs/labtop/variants/cml/board.fmd A src/mainboard/starlabs/labtop/variants/cml/data.vbt A src/mainboard/starlabs/labtop/variants/cml/devicetree.cb A src/mainboard/starlabs/labtop/variants/cml/devtree.c A src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/cml/gpio.c A src/mainboard/starlabs/labtop/variants/cml/hda_verb.c A src/mainboard/starlabs/labtop/variants/cml/romstage.c 19 files changed, 1,236 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 02383c9..c0442c4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -180,6 +180,7 @@ ## Star Labs Systems +- [LabTop Mk IV](starlabs/labtop_cml.md) - [StarLite Mk III](starlabs/lite_glk.md) - [StarBook Mk V](starlabs/starbook_tgl.md) diff --git a/Documentation/mainboard/starlabs/labtop_cml.md b/Documentation/mainboard/starlabs/labtop_cml.md new file mode 100644 index 0000000..2f70173 --- /dev/null +++ b/Documentation/mainboard/starlabs/labtop_cml.md @@ -0,0 +1,87 @@ +# Star LabTop Mk IV + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel i7-10710U (Comet Lake) + - Intel i3-10110U (Comet Lake) +- EC + - ITE IT8987E + - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - Charger, using AC adapter or USB-C PD + - Suspend / resume +- GPU + - Intel UHD Graphics 620 + - GOP driver is recommended, VBT is provided + - eDP 13-inch 1920x1080 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 16GB on-board *1 +- Networking + - AX201 CNVi WiFi / Bluetooth soldered to PCBA +- Sound + - Realtek ALC256 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1280x720 CCD camera + - USB 3.1 Gen 2 Type-C (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + +[^1] The Comet Lake PCB supports multiple memory variations that are based on hardware configuration resistors see `src/mainboard/starlabs/labtop/variants/cml/romstage.c` + +## Building coreboot + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml +make +``` + +## Flashing coreboot + +```eval_rst ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | 25Q128JVSQ | ++---------------------+------------+ +| Size | 16 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ + +Please see [here](../common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/labtop/Kconfig b/src/mainboard/starlabs/labtop/Kconfig index 6fe3446..1700fb1 100644 --- a/src/mainboard/starlabs/labtop/Kconfig +++ b/src/mainboard/starlabs/labtop/Kconfig @@ -13,6 +13,18 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SYSTEM_TYPE_LAPTOP +config BOARD_STARLABS_LABTOP_CML + select BOARD_ROMSIZE_KB_16384 + select BOARD_STARLABS_LABTOP_SERIES + select EC_STARLABS_NEED_ITE_BIN + select HAVE_INTEL_PTT + select HAVE_SPD_IN_CBFS + select MAINBOARD_HAS_CRB_TPM + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMETLAKE_1 + select SPI_FLASH_WINBOND + config BOARD_STARLABS_STARBOOK_TGL select BOARD_ROMSIZE_KB_16384 select BOARD_STARLABS_LABTOP_SERIES @@ -53,7 +65,8 @@ default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/\$(CONFIG_VARIANT_DIR)/ec.bin" config EC_VARIANT_DIR - default "tgl" if !EC_STARLABS_MERLIN + default "cml" if !EC_STARLABS_MERLIN && BOARD_STARLABS_LABTOP_CML + default "tgl" if !EC_STARLABS_MERLIN && BOARD_STARLABS_STARBOOK_TGL config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" @@ -67,13 +80,16 @@ config MAINBOARD_FAMILY string - default "B5" + default "L4" if BOARD_STARLABS_LABTOP_CML + default "B5" if BOARD_STARLABS_STARBOOK_TGL config MAINBOARD_PART_NUMBER - default "StarBook Mk V" + default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML + default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL config MAINBOARD_SMBIOS_PRODUCT_NAME - default "StarBook" + default "StarBook" if BOARD_STARLABS_STARBOOK_TGL + default "LabTop" config ME_BIN_PATH string @@ -87,9 +103,10 @@ default 2 config USE_PM_ACPI_TIMER - default n + default n if BOARD_STARLABS_STARBOOK_TGL config VARIANT_DIR - default "tgl" + default "cml" if BOARD_STARLABS_LABTOP_CML + default "tgl" if BOARD_STARLABS_STARBOOK_TGL endif diff --git a/src/mainboard/starlabs/labtop/Kconfig.name b/src/mainboard/starlabs/labtop/Kconfig.name index b3a5742..d00582f 100644 --- a/src/mainboard/starlabs/labtop/Kconfig.name +++ b/src/mainboard/starlabs/labtop/Kconfig.name @@ -1,4 +1,7 @@ comment "Star Labs LabTop Series" +config BOARD_STARLABS_LABTOP_CML + bool "Star Labs LabTop Mk IV (i3-10110U and i7-10710U)" + config BOARD_STARLABS_STARBOOK_TGL bool "Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)" diff --git a/src/mainboard/starlabs/labtop/Makefile.inc b/src/mainboard/starlabs/labtop/Makefile.inc index 71fc0cf..dc26be0 100644 --- a/src/mainboard/starlabs/labtop/Makefile.inc +++ b/src/mainboard/starlabs/labtop/Makefile.inc @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += ./spd subdirs-y += variants/$(VARIANT_DIR) bootblock-y += bootblock.c diff --git a/src/mainboard/starlabs/labtop/dsdt.asl b/src/mainboard/starlabs/labtop/dsdt.asl index ac6bc43..c43e048 100644 --- a/src/mainboard/starlabs/labtop/dsdt.asl +++ b/src/mainboard/starlabs/labtop/dsdt.asl @@ -17,10 +17,16 @@ Device (\_SB.PCI0) { +#if CONFIG(SOC_INTEL_CANNONLAKE_BASE) + /* Comet Lake */ + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> +#elif CONFIG(SOC_INTEL_TIGERLAKE) /* Tiger Lake */ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> +#endif /* PS/2 Keyboard */ #include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/starlabs/labtop/spd/Makefile.inc b/src/mainboard/starlabs/labtop/spd/Makefile.inc new file mode 100644 index 0000000..9e7f4e3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/Makefile.inc @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Schematics for this platform show Samsung K4A8G165WB-BCRC devices +# which are 8Gb, 2400Mbps 512Mx16 devices. +# +# The hardware platforms used for testing are fitted with a Micron part +# which has the FBGA identifier "D9ZFW". The identification tool at +# https://www.micron.com/support/tools-and-utilities/fbga identifies +# this as the MT40A1G16KD-062E:E. These are 16Gb, 1Gx16 devices. +# +# We have defined both SPD options below. +SPD_SOURCES = empty_ddr4 # 0b0000 +SPD_SOURCES += micron-MT40A1G16KD-062E-E # 0b0001 +SPD_SOURCES += empty_ddr4 # 0b0010 +SPD_SOURCES += empty_ddr4 # 0b0011 +SPD_SOURCES += empty_ddr4 # 0b0100 +SPD_SOURCES += empty_ddr4 # 0b0101 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0110 +SPD_SOURCES += samsung-K4A8G165WB-BCRC # 0b0111 + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/empty_ddr4.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex new file mode 100644 index 0000000..1777847 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/micron-MT40A1G16KD-062E-E.spd.hex @@ -0,0 +1,33 @@ +# Micron MT40A1G16KD-062E:E +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0 +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47 +31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex new file mode 100644 index 0000000..36b85a2 --- /dev/null +++ b/src/mainboard/starlabs/labtop/spd/samsung-K4A8G165WB-BCRC.spd.hex @@ -0,0 +1,33 @@ +# K4A8G165WB-BCRC +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 0B E3 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 42 42 30 2D 43 52 43 20 20 20 20 00 80 CE +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc new file mode 100644 index 0000000..2a505c3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/starlabs/labtop/variants/cml/board.fmd b/src/mainboard/starlabs/labtop/variants/cml/board.fmd new file mode 100644 index 0000000..9018104 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/board.fmd @@ -0,0 +1,14 @@ +# +# Manually defined FMD in order to ensure that space is reserved for the EC +# at the top of the BIOS region. +# +FLASH 16M { + BIOS@0x400000 0xC00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/data.vbt b/src/mainboard/starlabs/labtop/variants/cml/data.vbt new file mode 100644 index 0000000..4b31c96 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb new file mode 100644 index 0000000..c0077a4 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devicetree.cb @@ -0,0 +1,195 @@ +chip soc/intel/cannonlake + # CPU + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Graphics + # IGD Displays + register "panel_cfg" = "{ + .up_delay_ms = 0, // T3 + .backlight_on_delay_ms = 0, // T7 + .backlight_off_delay_ms = 0, // T9 + .down_delay_ms = 0, // T10 + .cycle_delay_ms = 500, // T12 + .backlight_pwm_hz = 200, // PWM + }" + + # FSP Memory + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + + # FSP Silicon + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + # Power + register "PchPmSlpS3MinAssert" = "2" # 50ms + register "PchPmSlpS4MinAssert" = "3" # 1s + register "PchPmSlpSusMinAssert" = "3" # 500ms + register "PchPmSlpAMinAssert" = "3" # 2s + + # Thermal + register "tcc_offset" = "10" + + # PM Util + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_B" + register "gpe0_dw1" = "PMC_GPP_C" + register "gpe0_dw2" = "PMC_GPP_E" + + # PCIe Clock + register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED" + +# Actual device tree. + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal Device + register "Device4Enable" = "1" + end + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on # USB xHCI + ### USB 2.0 Devices + # Motherboard USB Type C + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" + # Motherboard USB 3.0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + # Daughterboard SD Card + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" + # Daughterboard USB 3.0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" + # Internal Webcam + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" + # Internal Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" + + ### USB 3.0 Devices + # Motherboard USB Type C + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Motherboard USB 3.0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + # Daughterboard USB 3.0 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on # CNVi + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device pci 14.5 off end # SDCard + device pci 15.0 on # I2C0 + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device pci 15.1 off end # I2C1 + device pci 15.2 off end # I2C2 + device pci 15.3 off end # I2C3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 1 + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + end + device pci 19.0 on end # I2C4 + device pci 19.1 off end # I2C5 + device pci 19.2 on end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on # PCI Express Port 9 (SSD x4) + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[1]" = "0x08" + register "PcieClkSrcClkReq[1]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on # LPC Interface + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00fc0201" + register "gen4_dec" = "0x000c0081" + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device pci 1f.1 off end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on # Intel HDA + subsystemid 0x10ec 0x1200 + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end + chip drivers/crb + device mmio 0xfed40000 on end + end +end diff --git a/src/mainboard/starlabs/labtop/variants/cml/devtree.c b/src/mainboard/starlabs/labtop/variants/cml/devtree.c new file mode 100644 index 0000000..cf0734e --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/devtree.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_power_limits_config *soc_conf = &cfg->power_limits_config; + + struct device *nic_dev = pcidev_on_root(0x14, 3); + + /* Update PL1 & PL2 based on CMOS settings */ + switch (get_uint_option("power_profile", 0)) { + case 1: + soc_conf->tdp_pl1_override = 17; + soc_conf->tdp_pl2_override = 20; + break; + case 2: + soc_conf->tdp_pl1_override = 20; + soc_conf->tdp_pl2_override = 25; + break; + default: + disable_turbo(); + soc_conf->tdp_pl1_override = 15; + soc_conf->tdp_pl2_override = 15; + break; + } + + /* Enable/Disable Wireless based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + nic_dev->enabled = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[3].enable = 0; +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads new file mode 100644 index 0000000..8402b39 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gma-mainboard.ads @@ -0,0 +1,18 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, -- USB-C + HDMI1, -- USB-C + HDMI2, -- HDMI + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/starlabs/labtop/variants/cml/gpio.c b/src/mainboard/starlabs/labtop/variants/cml/gpio.c new file mode 100644 index 0000000..e29cd81 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/gpio.c @@ -0,0 +1,414 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* + * All definitions are taken from a comparison of the output of "inteltool -a" + * using the stock BIOS and with coreboot. + */ + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* C20: UART2_RXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* C21: UART2_TXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* E22: BRD_ID0 */ + PAD_CFG_GPO(GPP_E22, 1, PLTRST), + /* E23: BRD_ID1 */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* H6: BRD_ID2 */ + PAD_CFG_GPI(GPP_H6, NONE, PLTRST), + /* H7: BRD_ID3 */ + PAD_CFG_GPI(GPP_H7, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* REFERENCE: EP PER SCHEMATIC */ + + /* GPD0: PCH_BATLOW# */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: AC_PRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# */ + PAD_NC(GPD2, NONE), + /* GPD3: SIO_PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + /* GPD4: SIO_SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SIO_SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SIO_SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: PCH_TBT_PERST# */ + PAD_CFG_GPO(GPD7, 0, PLTRST), + /* GPD8: SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SIO_SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SIO_SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: PM_LANPHY_EN */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + + /* A0: KBRST_N */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + /* A1: LPC_AD0 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + /* A2: LPC_AD1 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + /* A3: LPC_AD2 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + /* A4: LPC_AD3 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + /* A5: LPC_FRAME_N */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + /* A6: LPC_SERIRQ */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + /* A7: Not Connected */ + PAD_NC(GPP_A7, NONE), + /* A8: GPPC_A8_CLKRUN_N */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9: ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* A10: Not Connected */ + PAD_NC(GPP_A10, NONE), + /* A11: Not Connected */ + PAD_NC(GPP_A11, NONE), + /* A12: TABLET_MODE_CTRL */ + PAD_NC(GPP_A12, NONE), + /* A13: SUSPWRDNACK */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* A14: PM_SUS_STAT_N */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15: SPK_PD_N */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + /* A16: Not Connected */ + PAD_NC(GPP_A16, NONE), + /* A17: SAR_DPR_PCH */ + PAD_NC(GPP_A17, NONE), + /* A18: ACCEL1_INT1 */ + PAD_NC(GPP_A18, UP_20K), + /* A19: ACCEL2_INT1 */ + PAD_NC(GPP_A19, UP_20K), + /* A20: HUMAN_PRESENCE_INT_N */ + PAD_NC(GPP_A20, UP_20K), + /* A21: HALL_SENSOR_INT */ + PAD_NC(GPP_A21, UP_20K), + /* A22: SAR_NIRQ_PCH */ + PAD_NC(GPP_A22, UP_20K), + /* A23: INT_SHARED */ + PAD_NC(GPP_A23, UP_20K), + + /* B0: Not Connected */ + PAD_NC(GPP_B0, NONE), + /* B1: Not Connected */ + PAD_NC(GPP_B1, NONE), + /* B2: Not Connected */ + PAD_NC(GPP_B2, NONE), + /* B3: CLICK_PAD_INT_R_N */ + PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, PLTRST), + /* B4: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* B5: WLAN_CLKREQ# */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6: CLKREQ1_SSD_N */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7: LAN_CLKREQ# */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8: Not Connected */ + PAD_NC(GPP_B8, NONE), + /* B9: Not Connected */ + PAD_NC(GPP_B9, NONE), + /* B10: Not Connected */ + PAD_NC(GPP_B10, NONE), + /* B11: EXT_PWR_GATE_N */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + /* B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: TCH_PNL_PWR_EN */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* B15: Not Connected */ + PAD_NC(GPP_B15, NONE), + /* B16: FPS_INT */ + PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), + /* B17: FPS_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + /* B18: AR_CIO_PWR_EN */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + /* B19: GSPI1_CS0_FPS_N */ + PAD_NC(GPP_B19, NONE), + /* B20: GSPI1_CLK_FPS */ + PAD_NC(GPP_B20, NONE), + /* B21: GSPI1_MISO_FPS */ + PAD_NC(GPP_B21, NONE), + /* B22: GSPI1_MOSI_FPS */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* B23: EC_SLP_S0IX_N */ + PAD_NC(GPP_B23, NONE), + + /* C0: SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* C1: SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C2: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + /* C3: Not Connected */ + PAD_NC(GPP_C3, NONE), + /* C4: Not Connected */ + PAD_NC(GPP_C4, NONE), + /* C5: SML0ALERT */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* C6: Not Connected */ + PAD_NC(GPP_C6, NONE), + /* C7: Not Connected */ + PAD_NC(GPP_C7, NONE), + /* C8: CODEC_INT_N */ + PAD_CFG_GPI_APIC_LOW(GPP_C8, UP_20K, PLTRST), + /* C9: Not Connected */ + PAD_NC(GPP_C9, NONE), + /* C10: Not Connected */ + PAD_NC(GPP_C10, NONE), + /* C11: Not Connected */ + PAD_NC(GPP_C11, NONE), + /* C12: PCIE_NAND_RST_R_N */ + PAD_CFG_GPO(GPP_C12, 1, PLTRST), + /* C13: M2_SSD_PWREN */ + PAD_NC(GPP_C13, NONE), + /* C14: TBT_WAKE_MUX_SEL_N */ + PAD_NC(GPP_C14, NONE), + /* C15: TBT_RST_N */ + PAD_NC(GPP_C15, NONE), + /* C16: I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17: I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18: TOUCH_I2C_SDA */ + PAD_NC(GPP_C18, NONE), + /* C19: TOUCH_I2C_SDL */ + PAD_NC(GPP_C19, NONE), + /* C22: AR1_USB_PWR_EN */ + PAD_NC(GPP_C22, NONE), + /* C23: Not Connected */ + PAD_NC(GPP_C23, NONE), + + /* D0: TPM_IRQ */ + PAD_NC(GPP_D0, NONE), + /* D1: Not Connected */ + PAD_NC(GPP_D1, NONE), + /* D2: Not Connected */ + PAD_NC(GPP_D2, NONE), + /* D3: Not Connected */ + PAD_NC(GPP_D3, NONE), + /* D4: Not Connected */ + PAD_NC(GPP_D4, NONE), + /* D5: Not Connected */ + PAD_NC(GPP_D5, NONE), + /* D6: Not Connected */ + PAD_NC(GPP_D6, NONE), + /* D7: ISH_I2C1_SDA */ + PAD_NC(GPP_D7, NONE), + /* D8: ISH_I2C1_SDL */ + PAD_NC(GPP_D8, NONE), + /* D9: TCH_PNL2_RST_R_N */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + /* D10: TCH_PNL2_INT_R_N */ + PAD_NC(GPP_D10, NATIVE), + /* D11: Not Connected */ + PAD_NC(GPP_D11, NATIVE), + /* D12: GPPC_D_12 */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), + /* D13: WWAN_FCP_OFF_N */ + PAD_NC(GPP_D13, NONE), + /* D14: TCH_PNL1_RST_N */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* D15: Not Connected */ + PAD_NC(GPP_D15, NONE), + /* D16: GPIO_2_EC */ + PAD_CFG_GPO(GPP_D16, 0, PWROK), + /* D17: DMIC_CLK1_SNDW3_CLK */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18: DMIC_DATA1_SNDW3_DATA */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* D19: DMIC_CLK_0 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* D20: DMIC_DATA_0 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21: Not Connected */ + PAD_NC(GPP_D21, NONE), + /* D22: TPM_RST */ + PAD_NC(GPP_D22, NONE), + /* D23: TPM_IRQ */ + PAD_NC(GPP_D23, NONE), + + /* E0: Not Connected */ + PAD_NC(GPP_E0, NONE), + /* E1: GPPC_E1_SATAXPCIE_1_SATAGP_1 */ + PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), + /* E2: Not Connected */ + PAD_NC(GPP_E2, NONE), + /* E3: Not Connected */ + PAD_NC(GPP_E3, NONE), + /* E4: Not Connected */ + PAD_NC(GPP_E4, NONE), + /* E5: GPPC_E5_SATA_DEVSLP_1 */ + PAD_NC(GPP_E5, NONE), + /* E6: Not Connected */ + PAD_NC(GPP_E6, NONE), + /* E7: Not Connected */ + PAD_CFG_GPI(GPP_E7, NONE, PLTRST), + /* E8: Not Connected */ + PAD_NC(GPP_E8, NONE), + /* E9: GPPC_E9_USB2_OCB_0 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10: GPPC_E10_USB2_OCB_1 */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11: USB2_P3_WP2_OC_N */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12: GPPC_E12_USB2_OCB_3 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13: DDI1_HPD */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E14: DDI2_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: SMC_SMI_N */ + PAD_CFG_GPI_SMI_LOW(GPP_E15, NONE, DEEP, EDGE_SINGLE), + /* E16: SMC_SCI_N */ + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, PLTRST, LEVEL), + /* E17: EDP_HPD */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* E18: DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* E19: DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* E20: DDI2_CTRL_CLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21: DDI2_CTRL_DATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F0: Not Connected */ + PAD_NC(GPP_F0, NONE), + /* F1: Not Connected */ + PAD_NC(GPP_F1, NONE), + /* F2: Not Connected */ + PAD_NC(GPP_F2, NONE), + /* F3: Not Connected */ + PAD_NC(GPP_F3, NONE), + /* F4: CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + /* F5: CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + /* F6: CNV_RGI_DT_R */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + /* F7: CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + /* F8: Not Connected */ + PAD_NC(GPP_F8, NONE), + /* F9: Not Connected */ + PAD_NC(GPP_F9, NONE), + /* F10: Not Connected */ + PAD_NC(GPP_F10, NONE), + /* F11: EMMC_CMD */ + PAD_NC(GPP_F11, NONE), + /* F12: EMMC_DATA_0 */ + PAD_NC(GPP_F12, NONE), + /* F13: EMMC_DATA_1 */ + PAD_NC(GPP_F13, NONE), + /* F14: EMMC_DATA_2 */ + PAD_NC(GPP_F14, NONE), + /* F15: EMMC_DATA_3 */ + PAD_NC(GPP_F15, NONE), + /* F16: EMMC_DATA_4 */ + PAD_NC(GPP_F16, NONE), + /* F17: EMMC_DATA_5 */ + PAD_NC(GPP_F17, NONE), + /* F18: EMMC_DATA_6 */ + PAD_NC(GPP_F18, NONE), + /* F19: EMMC_DATA_7 */ + PAD_NC(GPP_F19, NONE), + /* F20: EMMC_STROBE */ + PAD_NC(GPP_F20, NONE), + /* F21: EMMC_CLK */ + PAD_NC(GPP_F21, NONE), + /* F22: EMMC_RESETB */ + PAD_NC(GPP_F22, NONE), + /* F23: A4WP_PRESENT */ + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + + /* G0: Not Connected */ + PAD_NC(GPP_G0, NONE), + /* G1: Not Connected */ + PAD_NC(GPP_G1, NONE), + /* G2: Not Connected */ + PAD_NC(GPP_G2, NONE), + /* G3: Not Connected */ + PAD_NC(GPP_G3, NONE), + /* G4: Not Connected */ + PAD_NC(GPP_G4, NONE), + /* G5: Not Connected */ + PAD_NC(GPP_G5, UP_20K), + /* G6: Not Connected */ + PAD_NC(GPP_G6, NONE), + /* G7: Not Connected */ + PAD_NC(GPP_G7, DN_20K), + + /* H0: Not Connected */ + PAD_NC(GPP_H0, NONE), + /* H1: GPPC_H1_SSP2_SFRM */ + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + /* H2: GPPC_H2_SSP2_TXD */ + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + /* H3: Not Connected */ + PAD_NC(GPP_H3, UP_20K), + /* H4: GSENSOR_I2C_SDA */ + PAD_NC(GPP_H4, NONE), + /* H5: GSENSOR_I2C_SCL */ + PAD_NC(GPP_H5, NONE), + /* H8: Not Connected */ + PAD_NC(GPP_H8, NONE), + /* H9: Not Connected */ + PAD_NC(GPP_H9, NONE), + /* H10: ISH_I2C2_SDA */ + PAD_CFG_GPO(GPP_H10, 1, PLTRST), + /* H11: ISH_I2C2_SCL */ + PAD_CFG_GPO(GPP_H11, 1, PLTRST), + /* H12: Not Connected */ + PAD_NC(GPP_H12, NONE), + /* H13: Not Connected */ + PAD_NC(GPP_H13, NONE), + /* H14: Not Connected */ + PAD_NC(GPP_H14, NONE), + /* H15: Not Connected */ + PAD_NC(GPP_H15, NONE), + /* H16: Not Connected */ + PAD_NC(GPP_H16, NONE), + /* H17: GPPC_H_17_WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* H18: GPPC_H_18_CPU_C10 */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19: Not Connected */ + PAD_NC(GPP_H19, NONE), + /* H20: Not Connected */ + PAD_NC(GPP_H20, NONE), + /* H21: GPPC_H21 */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + /* H22: Not Connected */ + PAD_NC(GPP_H22, NONE), + /* H23: GPPC_H23 */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c new file mode 100644 index 0000000..76762a5 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/hda_verb.c @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec1200, /* Subsystem ID */ + 38, /* Number of jacks (NID entries) */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x10ec1200), + + /* Pin Widget Verb-table */ + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, 0x12, 0x90a61120), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90171110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x40700001), + AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x042b1010), + + /* Reset to D0 */ + 0x00170500, + 0x00170500, + 0x00170500, + 0x00170500, + + /* Reset Register */ + 0x0205001A, + 0x02048003, + 0x0205001A, + 0x0204C003, + + /* ALC256 Default 1 */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + + /* ALC256 Default 2 */ + 0x02050040, + 0x02049800, + 0x02050034, + 0x0204023C, + + /* ALC256 Default 3 */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + + /* ALC256 Default 4 */ + 0x0205001B, + 0x02040A4B, + 0x02050008, + 0x02046A6C, + + /* Jack Detection */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + + /* Combo Jack TRS setting */ + 0x02050038, + 0x02047901, + + /* Disable Microphone Security */ + 0x0205000D, + 0x0204A020, + + /* Enable ADC clock */ + 0x02050005, + 0x02040700, + + /* Speaker Enable */ + 0x0205000C, + 0x020401EF, + + /* + * Equalizer: + * + * AGC + * Threshold: - 6.00 dB + * Front Boost: + 6.00 dB + * Post Boost: + 6.00 dB + * + * Low Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: + 4.00 dB + * + * Band Pass Filter 1 + * Fc: 240Hz + * BW: 400Hz + * Gain: - 4.00 dB + * + * Band Pass Filter 2 + * Fc: 16000Hz + * BW: 1000Hz + * Gain: + 12.00 dB + * + * High Pass Filter + * Boost Gain: Enabled + * BW: 200Hz + * Gain: - 4.00 dB + * + * Class D Amp + * Power: 2.5W + * Resistance: 4ohms + * + * EQ Output + * Left: + 0.00 dB + * Right: + 0.00 dB + * + * VARQ + * Q: 0.707 + */ + + 0x05350000, + 0x053404DA, + 0x0535001d, + 0x05340800, + + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341F7A, + + 0x05350004, + 0x0534FA18, + 0x0535000F, + 0x0534C295, + + 0x05350010, + 0x05341D73, + 0x05350011, + 0x0534FA18, + + 0x05350012, + 0x05341E08, + 0x05350013, + 0x05341C10, + + 0x05350014, + 0x05342FB2, + 0x0535001B, + 0x05341F2C, + + 0x0535001C, + 0x0534095C, + 0x05450000, + 0x05440000, + + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + + 0x05450003, + 0x05441F7A, + 0x05450004, + 0x0544FA18, + + 0x0545000F, + 0x0544C295, + 0x05450010, + 0x05441D73, + + 0x05450011, + 0x0544FA18, + 0x05450012, + 0x05441E08, + + 0x05450013, + 0x05441C10, + 0x05450014, + 0x05442FB2, + + 0x0545001B, + 0x05441F2C, + 0x0545001C, + 0x0544095C, + + 0x05350000, + 0x0534C4DA, + 0x02050038, + 0x02044901, + + 0x02050013, + 0x0204422F, + 0x02050016, + 0x02044E50, + + 0x02050012, + 0x0204EBC4, + 0x02050020, + 0x020451FF, + + 0x8086280b, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/labtop/variants/cml/romstage.c b/src/mainboard/starlabs/labtop/variants/cml/romstage.c new file mode 100644 index 0000000..189b7f3 --- /dev/null +++ b/src/mainboard/starlabs/labtop/variants/cml/romstage.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <gpio.h> +#include <option.h> +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <string.h> +#include <types.h> + +static unsigned int get_memory_config_straps(void) +{ + /* + * The hardware supports a number of different memory configurations + * which are selected using four ID bits ID3 (GPP_H7), ID2 (GPP_H6), + * ID1 (GPP_E23) and ID0 (GPP_E22). + * + * The mapping is defined in the schematics as follows (ID3 is always + * 0 and can be ignored): + * + * ID2 ID1 ID0 Memory type + * ----------------------------------------------- + * 0 0 0 Hynix 16G dual channel + * 0 0 1 Micron 16G dual channel + * 0 1 0 Hynix 8G dual channel + * 0 1 1 Hynix 4G single channel + * 1 0 0 Micron 8G dual channel + * 1 0 1 Micron 4G single channel + * 1 1 0 Samsung 8G dual channel + * 1 1 1 Samsung 4G single channel + * + * We return the value of these bits so that the index into the SPD + * table can be .spd[] values can be configured correctly in the + * memory configuration structure. + */ + + gpio_t memid_gpios[] = {GPP_E22, GPP_E23, GPP_H6}; + return (u8)gpio_base2_value(memid_gpios, ARRAY_SIZE(memid_gpios)); +} + +static bool is_dual_channel(const unsigned int memid) +{ + return memid != 3 && memid != 5 && memid != 7; +} + +static void fill_spd_data(struct cnl_mb_cfg *mem_cfg) +{ + const unsigned int memid = get_memory_config_straps(); + printk(BIOS_DEBUG, "Memory config straps: 0x%.2x\n", memid); + /* + * If we are using single channel ID = 3, 5 or 7 then we only + * populate .spd[0].If we are dual channel then we also populate + * .spd[2] as well. + */ + mem_cfg->spd[0].read_type = READ_SPD_CBFS; + mem_cfg->spd[0].spd_spec.spd_index = memid; + if (is_dual_channel(memid)) { + mem_cfg->spd[2].read_type = READ_SPD_CBFS; + mem_cfg->spd[2].spd_spec.spd_index = memid; + } +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + struct cnl_mb_cfg memcfg = { + .rcomp_resistor = {121, 81, 100}, + .rcomp_targets = {100, 40, 20, 20, 26}, + .dq_pins_interleaved = 0, + .vref_ca_config = 2, + .ect = 0, + }; + + const uint8_t vtd = get_uint_option("vtd", 1); + memupd->FspmTestConfig.VtdDisable = !vtd; + + const uint8_t ht = + get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); + memupd->FspmConfig.HyperThreading = ht; + + fill_spd_data(&memcfg); + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/58428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbaa907dc38dc521961806132f21b7a90324ec9c Gerrit-Change-Number: 58428 Gerrit-PatchSet: 100 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Add weak SoC and mainboard init and exit methods
by Raul Rangel (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Martin Roth, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62500 ) Change subject: cpu/x86/smm: Add weak SoC and mainboard init and exit methods ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: > Oops, forgot to uncheck the resolved box. What do you mean? File src/include/cpu/x86/smm.h: https://review.coreboot.org/c/coreboot/+/62500/comment/89a2c50b_7087c2ad PS3, Line 55: void smm_mainboard_early_init(void); : void smm_mainboard_exit(void); > In the subsequent patchset, we use only SoC hooks. […] Sure, we can add the mainboard methods later if we need them. I'll push up a new patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I946619cd62a974a98c575a92943b43ea639fc329 Gerrit-Change-Number: 62500 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem
by Raul Rangel (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Rob Barnes, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62402 ) Change subject: soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmem ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/common/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62402/comment/e58d6e2c_47b3c89d PS6, Line 15: $(src)/soc/amd/common/vboot/early_ram_symbols.awk > I think the error message might be more readable if this is left off. […] Which error message? We need to add it as a dep, otherwise changing the .awk won't cause the .ld file to be rebuilt. I'm not sure if there is a helper to map the current directory. i.e., $(src-to-obj) -- To view, visit https://review.coreboot.org/c/coreboot/+/62402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Gerrit-Change-Number: 62402 Gerrit-PatchSet: 6 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:47:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Configure WLAN
by Raul Rangel (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jon Murphy, Paul Menzel. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62165 ) Change subject: mb/google/skyrim: Configure WLAN ...................................................................... Patch Set 30: (2 comments) File src/mainboard/google/skyrim/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/62165/comment/b2703d38_324ee442 PS30, Line 161: WLAN_DISABLE Should we set this in the early table as well? https://review.coreboot.org/c/coreboot/+/62165/comment/fd678379_c2189cad PS30, Line 180: PAD_NFO Hrmm, I thought we were deasserting this in the early table. -- To view, visit https://review.coreboot.org/c/coreboot/+/62165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Gerrit-Change-Number: 62165 Gerrit-PatchSet: 30 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:42:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/google/chromeos/Kconfig: Fix typo
by Felix Held (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Angel Pons. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62661 ) Change subject: vc/google/chromeos/Kconfig: Fix typo ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5cbd77a156852e6f8ad6eafc316ee33f153635b4 Gerrit-Change-Number: 62661 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:42:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add support to generate code under companion de...
by Tim Wawrzynczak (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Raul Rangel, Nico Huber, Selma Bensaid, Paul Menzel, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62301 ) Change subject: drivers/pcie/generic: Add support to generate code under companion device instead ...................................................................... Patch Set 7: (1 comment) Patchset: PS5: > Basically, yes. little background: […] Any other thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/62301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Gerrit-Change-Number: 62301 Gerrit-PatchSet: 7 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:30:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/bsd: Remove cb_err_t
by Tim Wawrzynczak (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Jakub Czapiga, Julius Werner, Tim Wawrzynczak, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62600 ) Change subject: commonlib/bsd: Remove cb_err_t ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Gerrit-Change-Number: 62600 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:29:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting
by Tim Wawrzynczak (Code Review) 08 Mar '22

08 Mar '22

Attention is currently required from: Dtrain Hsu, Nick Vaccaro, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC PL2/PL4 default setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 08 Mar 2022 15:28:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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