coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Cliff Huang (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Tim Wawrzynczak. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62330 ) Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62330/comment/f5296d8e_0cc4b72f PS10, Line 213: rp6_wwan > Oh wait, don't we want […] hum... pcie_rp6 is the parent device, while wwan is the companion device, which creates 'PXSX' device. There is always parent device with a pcie generic, but not necessary have other device attaching to the same root port. The idea is to point to the device whichever create the device object, if there is one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 00:17:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: commonlib/timestamp_serialized: Add timestamp enum to name mapping
by Julius Werner (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62709 ) Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping ...................................................................... Patch Set 3: (2 comments) File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/c/coreboot/+/62709/comment/2e8e2a24_7cb0401e PS3, Line 316: #define ts_str(x) #x You can use STRINGIFY() from <string.h> https://review.coreboot.org/c/coreboot/+/62709/comment/e0e3c06f_77e7a87f PS3, Line 319: static const struct timestamp_id_to_enum_name { Let's merge this together with the other table so we don't need to have two separate tables? -- To view, visit https://review.coreboot.org/c/coreboot/+/62709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Gerrit-Change-Number: 62709 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 00:15:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Configure WLAN
by 9elements QA (Code Review) 11 Mar '22

11 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62165 ) Change subject: mb/google/skyrim: Configure WLAN ...................................................................... Patch Set 31: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95188 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95187 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/95186 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/95185 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/95184 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95183 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/95182 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/95181 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/95180 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/95179 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/95178 FAIL: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/95177 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95176 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/95175 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/95174 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/95173 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Gerrit-Change-Number: 62165 Gerrit-PatchSet: 31 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 00:06:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: i2c: Add configurable I2C transfer timeout
by Jes Klinke (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Hung-Te Lin, Felix Singer, Patrick Rudolph. Jes Klinke has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62278 ) Change subject: i2c: Add configurable I2C transfer timeout ...................................................................... Patch Set 8: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62278/comment/22a94f71_9687d58f PS7, Line 7: Configurable > Add configurable ... Done Patchset: PS8: I have updated the commit message based on comments, and to state the rationale for changing the timeouts across the board. File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/62278/comment/81327af7_a4e10d25 PS7, Line 242: CONFIG_I2C_TRANSFER_TIMEOUT_US > I would suggest we change all affected timeouts to the new default unless someone has an explicit re […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Gerrit-Change-Number: 62278 Gerrit-PatchSet: 8 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Qii Wang <qii.wang(a)mediatek.corp-partner.google.com> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:59:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/generic: Add support to generate code under companion de...
by Felix Held (Code Review) 11 Mar '22

11 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62301 ) Change subject: drivers/pcie/generic: Add support to generate code under companion device instead ...................................................................... drivers/pcie/generic: Add support to generate code under companion device instead Only one ACPI device should be added to a PCIe root port. For the root ports which already have device created, the generated code from this driver needs to be merged with the existing device. By default, this driver will create new device named DEV0. This change allows to generate code under an existing device. ex: (generate code under PXSX): Scope (\_SB.PCI0.RP01.PXSX) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package (0x01) { Package (0x02) { "UntrustedDevice", One } } }) } BUG=b:221250331 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62301 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/pcie/generic/chip.h M src/drivers/pcie/generic/generic.c 2 files changed, 27 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/drivers/pcie/generic/chip.h b/src/drivers/pcie/generic/chip.h index 3be57de..5d762ec 100644 --- a/src/drivers/pcie/generic/chip.h +++ b/src/drivers/pcie/generic/chip.h @@ -7,6 +7,14 @@ struct drivers_pcie_generic_config { bool is_untrusted; + /* + * This needs to be pointed to the device instance in the device tree when + * there is already a device with the root port so that the ACPI code to be + * generated will be added to that existing device. + * By default, an ACPI device named 'DEV0' is created under the root port if + * this does not reference to a device. + */ + DEVTREE_CONST struct device *companion_dev; }; #endif /* _PCIE_GENERIC_H_ */ diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c index c14628f..0a9a243 100644 --- a/src/drivers/pcie/generic/generic.c +++ b/src/drivers/pcie/generic/generic.c @@ -9,6 +9,10 @@ static const char *pcie_generic_acpi_name(const struct device *dev) { + struct drivers_pcie_generic_config *config = dev->chip_info; + + if (config->companion_dev) + return acpi_device_name(config->companion_dev); return "DEV0"; } @@ -26,22 +30,29 @@ if (!config || !config->is_untrusted || !dev->bus || !dev->bus->dev) return; - const char *scope = acpi_device_path(dev->bus->dev); - const char *name = acpi_device_name(dev); + const char *scope; + const char *name; + /* Code will be generated under companion device instead if present. */ + if (config->companion_dev) + scope = acpi_device_path(config->companion_dev); + else + scope = acpi_device_path(dev->bus->dev); + name = acpi_device_name(dev); acpigen_write_scope(scope); - acpigen_write_device(name); - acpigen_write_ADR_pci_device(dev); - + if (!config->companion_dev) { + acpigen_write_device(name); + acpigen_write_ADR_pci_device(dev); + } dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_integer(dsd, "DmaProperty", 1); acpi_dp_write(dsd); - - acpigen_write_device_end(); + if (!config->companion_dev) + acpigen_write_device_end(); acpigen_write_scope_end(); printk(BIOS_INFO, "%s.%s: Enable ACPI properties for %s (%s)\n", scope, name, - dev_path(dev), dev->chip_ops->name); + dev_path(dev), dev->chip_ops->name); } struct device_operations pcie_generic_ops = { 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Gerrit-Change-Number: 62301 Gerrit-PatchSet: 9 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/pcie/generic: Add support to generate code under companion de...
by Felix Held (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Raul Rangel, Nico Huber, Selma Bensaid, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62301 ) Change subject: drivers/pcie/generic: Add support to generate code under companion device instead ...................................................................... Patch Set 8: (1 comment) Patchset: PS5: > Any other thoughts? can't say that i like this too much, but now i at least understand the problem this solves and don't see a much better approach that's not too invasive, so i won't object to this solution -- To view, visit https://review.coreboot.org/c/coreboot/+/62301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80634bbfc2927f26f2a55a9c244eca517c437079 Gerrit-Change-Number: 62301 Gerrit-PatchSet: 8 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:57:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: i2c: Add configurable I2C transfer timeout
by Jes Klinke (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Jes Klinke, Patrick Rudolph. Hello Hung-Te Lin, build bot (Jenkins), Julius Werner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62278 to look at the new patch set (#8). Change subject: i2c: Add configurable I2C transfer timeout ...................................................................... i2c: Add configurable I2C transfer timeout This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> --- M src/device/Kconfig M src/drivers/i2c/designware/dw_i2c.c M src/soc/cavium/cn81xx/twsi.c M src/soc/intel/quark/i2c.c M src/soc/mediatek/common/i2c.c M src/soc/qualcomm/common/include/soc/qup_se_handlers_common.h M src/soc/qualcomm/common/qup_se_handler.c M src/soc/qualcomm/common/qupv3_i2c.c M src/soc/qualcomm/common/qupv3_spi.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/qcs405/qup.c M src/soc/rockchip/common/i2c.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5420/i2c.c 15 files changed, 118 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62278/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/62278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Gerrit-Change-Number: 62278 Gerrit-PatchSet: 8 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Qii Wang <qii.wang(a)mediatek.corp-partner.google.com> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in qc_blobs[master]: sc7180/boot : Update qclib blobs binaries and release notes
by Julius Werner (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Sudheer Amrabadi. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/62734 ) Change subject: sc7180/boot : Update qclib blobs binaries and release notes ...................................................................... Patch Set 1: (1 comment) File sc7180/boot/Release_Notes.txt: https://review.coreboot.org/c/qc_blobs/+/62734/comment/c36bc3c7_091e03fa PS1, Line 6: 00037 Why is this 00037? The last version that's available to us on Chipcode is BOOT.XF.3.1.c4-00036-SC7180LCB-1. What's the difference? -- To view, visit https://review.coreboot.org/c/qc_blobs/+/62734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: qc_blobs Gerrit-Branch: master Gerrit-Change-Id: I1dace0db7fd1dcd2f34302885e3fec40b63b7eaf Gerrit-Change-Number: 62734 Gerrit-PatchSet: 1 Gerrit-Owner: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:51:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: console: Add loglevel prefix to interactive consoles
by Julius Werner (Code Review) 11 Mar '22

11 Mar '22

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61306 ) Change subject: console: Add loglevel prefix to interactive consoles ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > Julius, did you also send a patch to the Linux kernel for the driver/module memconsole-coreboot? Not yet although it's somewhere on my list of things I want to do when I find the time. If someone else wants to take care of that, I'd certainly appreciate it! -- To view, visit https://review.coreboot.org/c/coreboot/+/61306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Gerrit-Change-Number: 61306 Gerrit-PatchSet: 8 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:45:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cbmem: Fix console banner matches
by Julius Werner (Code Review) 11 Mar '22

11 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62720 ) Change subject: cbmem: Fix console banner matches ...................................................................... cbmem: Fix console banner matches Since the new loglevel markers were added, there will now be a marker character at the beginning of the coreboot banner string, and this will make the existing regular expressions meant to find it fail to match. This patch fixes the problem by just allowing for a single extra character there (any character to avoid the hassle of having to match the marker explicitly). The extra character is optional so that we will still continue to match banners from older versions of coreboot as well. Since the `?` glyph is not available in basic POSIX regular expressions, we have to switch to REG_EXTENDED syntax (should otherwise make no difference). (Also, move side effects out of assert() while I'm here, that's not actually safe for the standard libc implementation.) Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/cbmem/cbmem.c 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index a39ef2a..eef68a0 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -818,8 +818,8 @@ cursor = previous = 0; if (type != CONSOLE_PRINT_FULL) { #define BANNER_REGEX(stage) \ - "\n\ncoreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" -#define OVERFLOW_REGEX(stage) "\n\\*\\*\\* Pre-CBMEM " stage " console overflow" + "\n\n.?coreboot-[^\n]* " stage " starting.*\\.\\.\\.\n" +#define OVERFLOW_REGEX(stage) "\n.?\\*\\*\\* Pre-CBMEM " stage " console overflow" const char *regex[] = { BANNER_REGEX("verstage-before-bootblock"), BANNER_REGEX("bootblock"), BANNER_REGEX("verstage"), @@ -831,7 +831,8 @@ for (size_t i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { regex_t re; regmatch_t match; - assert(!regcomp(&re, regex[i], 0)); + int res = regcomp(&re, regex[i], REG_EXTENDED); + assert(res == 0); /* Keep looking for matches so we find the last one. */ while (!regexec(&re, console_c + cursor, 1, &match, 0)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/62720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975 Gerrit-Change-Number: 62720 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022