coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/wifi/generic: Add ops to generic cnvi device
by Tim Wawrzynczak (Code Review) 11 Mar '22

11 Mar '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62746 ) Change subject: drivers/wifi/generic: Add ops to generic cnvi device ...................................................................... drivers/wifi/generic: Add ops to generic cnvi device When adding properties to the Intel CNVi devices, a chip driver and a generic device are added underneath to contain the chip config properties. Currently there are no ops for this, and so a BIOS_ERR is printed that there is a device with no `read_resources` callback, which is true. Therefore, this patch adds a noop ops to this generic device. BUG=b:220639445 TEST=error message about a GENERIC 0.0 device missing read_resources is gone. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 --- M src/drivers/wifi/generic/generic.c 1 file changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/62746/1 diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index a6936f1..bfc161c 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -21,6 +21,7 @@ .enable_resources = pci_dev_enable_resources, .init = wifi_pci_dev_init, .ops_pci = &pci_dev_ops_pci, + .scan_bus = scan_static_bus, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = wifi_pcie_acpi_name, .acpi_fill_ssdt = wifi_pcie_fill_ssdt, @@ -61,17 +62,19 @@ return config->enable_cnvi_ddr_rfim; } +struct device_operations wifi_generic_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + static void wifi_generic_enable(struct device *dev) { - DEVTREE_CONST struct drivers_wifi_generic_config *config = dev ? dev->chip_info : NULL; - - if (!config) - return; - #if !DEVTREE_EARLY - if (is_cnvi(dev)) + if (dev->path.type == DEVICE_PATH_GENERIC) + dev->ops = &wifi_generic_ops; + else if (is_cnvi(dev)) dev->ops = &wifi_cnvi_ops; - else + else if (dev->path.type == DEVICE_PATH_PCI) dev->ops = &wifi_pcie_ops; #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/62746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Gerrit-Change-Number: 62746 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table
by Felix Held (Code Review) 11 Mar '22

11 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59507 ) Change subject: soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table ...................................................................... soc/intel/alderlake: Inject CSE TS into CBMEM timestamp table Get boot performance timestamps from CSE and inject them into CBMEM timestamp table after normalizing to the zero-point value. Although consumer CSE sku also supports this feature, it was validated on CSE Lite sku only. BUG=b:182575295 TEST=Able to see TS elapse prior to IA reset on Brya/Redrix 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 88,000 945:CSE started to handle ICC configuration 88,000 (0) 946:CSE sent 'Host BIOS Prep Done' to PMC 90,000 (2,000) 947:CSE received 'CPU Reset Done Ack sent' from PMC 282,000 (192,000) 0:1st timestamp 330,857 (48,857) 11:start of bootblock 341,811 (10,953) 12:end of bootblock 349,299 (7,487) Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59507 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 92 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 9720d9e..45421c8 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -142,6 +142,10 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } + /* Update coreboot timestamp table with CSE timestamps */ + if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY)) + cse_get_telemetry_data(); + /* * Set low maximum temp threshold value used for dynamic thermal sensor * shutdown consideration. diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index e302447..9621e9a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -166,6 +166,13 @@ help Enable compression on Intel CSE CBFS RW blob +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + def_bool n + depends on SOC_INTEL_CSE_LITE_SKU + help + Mainboard user to select this Kconfig in order to capture pre-cpu + reset boot performance telemetry data. + if STITCH_ME_BIN config CSE_COMPONENTS_PATH diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 472ae95..0c307ca 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -6,6 +6,7 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c ifeq ($(CONFIG_STITCH_ME_BIN),y) diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c new file mode 100644 index 0000000..544de80 --- /dev/null +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/cse.h> +#include <timestamp.h> + +#define MSEC_TO_USEC(x) (x * 1000) + +void cse_get_telemetry_data(void) +{ + struct cse_boot_perf_rsp cse_perf_data; + s64 ts[NUM_CSE_BOOT_PERF_DATA] = {0}; + s64 current_time, start_stamp; + int zero_point_idx = 0; + + /* + * 1. Each TS holds the time elapsed between the "Zero-Point" till the TS itself + * happened. + * 2. In case CSME did not hit some of the TS in the latest boot flow that value of + * these TS will be 0x00000000. + * 3. In case of error, TS value will be set to 0xFFFFFFFF. + * 4. All other TS values will be relative to the zero point. The API caller should + * normalize the TS values to the zero-point value. + */ + if (!cse_get_boot_performance_data(&cse_perf_data)) + return; + + current_time = timestamp_get(); + + for (unsigned int i = 0; i < NUM_CSE_BOOT_PERF_DATA; i++) { + + if (cse_perf_data.timestamp[i] == 0xffffffff) { + printk(BIOS_ERR, "%s: CSME timestamps invalid\n", __func__); + return; + } + + ts[i] = (s64)MSEC_TO_USEC(cse_perf_data.timestamp[i]) * + timestamp_tick_freq_mhz(); + } + + /* Find zero-point */ + for (unsigned int i = 0; i < NUM_CSE_BOOT_PERF_DATA; i++) { + if (cse_perf_data.timestamp[i] != 0) { + zero_point_idx = i; + break; + } + } + + /* Normalize TS values to zero-point */ + for (unsigned int i = zero_point_idx + 1; i < NUM_CSE_BOOT_PERF_DATA; i++) { + + if (ts[i] && ts[i] < ts[zero_point_idx]) { + printk(BIOS_ERR, "%s: CSME timestamps invalid," + " wraparound detected\n", __func__); + return; + } + + if (ts[i]) + ts[i] -= ts[zero_point_idx]; + } + + /* Inject CSME timestamps into the coreboot timestamp table */ + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f031ad5..f94fc73 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -509,4 +509,10 @@ */ void soc_disable_heci1_using_pcr(void); +/* + * Get all the timestamps CSE collected using cse_get_boot_performance_data() and + * insert them into the CBMEM timestamp table. + */ +void cse_get_telemetry_data(void); + #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/59507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbb69538ca2977cd97ce1ef9b211ff6510a3f8 Gerrit-Change-Number: 59507 Gerrit-PatchSet: 20 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Configure WLAN
by Felix Held (Code Review) 11 Mar '22

11 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62165 ) Change subject: mb/google/skyrim: Configure WLAN ...................................................................... mb/google/skyrim: Configure WLAN Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN. Mappping derived from Skyrim schematic. BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/Kconfig A src/mainboard/google/skyrim/romstage.c M src/mainboard/google/skyrim/variants/baseboard/Makefile.inc M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h 6 files changed, 51 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index b21291e..a036fa5 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -20,6 +20,7 @@ select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_WIFI_GENERIC select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_ESPI select ELOG diff --git a/src/mainboard/google/skyrim/romstage.c b/src/mainboard/google/skyrim/romstage.c new file mode 100644 index 0000000..bd7af6a --- /dev/null +++ b/src/mainboard/google/skyrim/romstage.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/platform_descriptors.h> + +void mb_pre_fspm(void) +{ + size_t base_num_gpios; + const struct soc_amd_gpio *base_gpios; + + /* Initialize PCIe reset. */ + variant_pcie_gpio_table(&base_gpios, &base_num_gpios); + + gpio_configure_pads(base_gpios, base_num_gpios); +} diff --git a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc index 7c092e4..dc1c1fe 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/skyrim/variants/baseboard/Makefile.inc @@ -1,5 +1,7 @@ bootblock-y += gpio.c +romstage-y += gpio.c + ramstage-y += gpio.c smm-y += gpio.c diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index c802868..ac9bd2be 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,7 +47,12 @@ device pnp 0c09.0 alias chrome_ec on end end end - device ref gpp_bridge_0 on end # WLAN + device ref gpp_bridge_0 on # WLAN + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end device ref gpp_bridge_1 on end # SD device ref gpp_bridge_2 on end # WWAN device ref gpp_bridge_3 on end # NVMe diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index dd30475..f095651 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -155,16 +155,37 @@ /* TODO: Fill sleep gpio configuration */ }; -/* Early GPIO configuration in bootblock */ +/* GPIO configuration in bootblock */ static const struct soc_amd_gpio bootblock_gpio_table[] = { - /* TODO: Fill bootblock gpio configuration */ + /* Enable WLAN */ + /* WLAN_DISABLE */ + PAD_GPO(GPIO_21, LOW), }; /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { - /* TODO: Fill early gpio configuration */ + /* WLAN_AUX_RESET_L (ACTIVE LOW) */ + PAD_GPO(GPIO_7, LOW), + /* Power on WLAN */ + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_9, HIGH), }; +/* PCIE_RST needs to be brought high before FSP-M runs */ +static const struct soc_amd_gpio pcie_gpio_table[] = { + /* Deassert all AUX_RESET lines & PCIE_RST */ + /* WLAN_AUX_RESET_L (ACTIVE LOW) */ + PAD_GPO(GPIO_7, HIGH), + /* PCIE_RST0_L */ + PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), +}; + +__weak void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) +{ + *size = ARRAY_SIZE(pcie_gpio_table); + *gpio = pcie_gpio_table; +} + __weak void variant_base_gpio_table(const struct soc_amd_gpio **gpio, size_t *size) { *size = ARRAY_SIZE(base_gpio_table); diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h index a99dd26..0fa3491 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h @@ -34,4 +34,7 @@ /* This function provides GPIO settings for TPM i2c bus. */ void variant_tpm_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); +/* This function provides GPIO settings before PCIe enumeration. */ +void variant_pcie_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); + #endif /* __BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2 Gerrit-Change-Number: 62165 Gerrit-PatchSet: 31 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim:Update GPIO 32
by Felix Held (Code Review) 11 Mar '22

11 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62717 ) Change subject: mb/google/skyrim:Update GPIO 32 ...................................................................... mb/google/skyrim:Update GPIO 32 GPIO 32 was not allocated correctly, updating to reflect the native function use of the pin BUG=b:214412172 TEST=Builds Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index 16a03ba..dd30475 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -65,7 +65,7 @@ /* Unused */ PAD_NC(GPIO_31), /* LPC_RST_L */ - PAD_GPO(GPIO_32, LOW), + PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), /* GPIO_33 - GPIO_39: Not available */ /* SOC_TCHPAD_INT_ODL */ PAD_SCI(GPIO_40, PULL_NONE, EDGE_LOW), -- To view, visit https://review.coreboot.org/c/coreboot/+/62717 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40 Gerrit-Change-Number: 62717 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
by Kangheui Won (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Eric Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62722 ) Change subject: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Gerrit-Change-Number: 62722 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:19:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell
by Tim Wawrzynczak (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Robert Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell ...................................................................... Patch Set 18: Code-Review+1 (1 comment) Patchset: PS18: > FYI the RP devices are moving in CB:62330 like the RP RTD3, do you want to just move it now? -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 18 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:19:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Tim Wawrzynczak (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Bora Guvendik, Cliff Huang, Selma Bensaid. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62330 ) Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... Patch Set 10: Code-Review+1 (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62330/comment/5af09b11_6dc391a9 PS10, Line 213: rp6_wwan Oh wait, don't we want `pcie_rp6` here? so that the property is under \_SB.PCI0.RP6 ? It is supposed to be the root port and the device itself, so I would expect RP6 and then \_SB.PCI0.RP6.PXSX I already added support to the WWAN driver itself, see https://review.coreboot.org/c/coreboot/+/62436/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:18:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell
by Tim Wawrzynczak (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Robert Chen, Shon Wang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61847 ) Change subject: mb/google/brya/var/vell: Add 5G WWAN ACPI support for vell ...................................................................... Patch Set 18: (1 comment) Patchset: PS18: FYI the RP devices are moving in CB:62330 -- To view, visit https://review.coreboot.org/c/coreboot/+/61847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be Gerrit-Change-Number: 61847 Gerrit-PatchSet: 18 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
by Cliff Huang (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Bora Guvendik, Selma Bensaid. Hello Bora Guvendik, build bot (Jenkins), Cliff Huang, Selma Bensaid, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62744 to look at the new patch set (#2). Change subject: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants ...................................................................... mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants This sets EPP value to be 45% for all Adl RVP variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/62744/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62744 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Gerrit-Change-Number: 62744 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code
by Tim Wawrzynczak (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Subrata Banik, Nick Vaccaro, Patrick Rudolph, Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62738 ) Change subject: {mb, soc}: Move mrc_cache invalidating logic into `memory` common code ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62738 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Gerrit-Change-Number: 62738 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 10 Mar 2022 23:07:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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