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Change subject: soc/intel/common: Pass `FSPM_UPD *` argument for spd functions
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/soc/intel/common/block/include/intelblocks/meminit.h:
https://review.coreboot.org/c/coreboot/+/62737/comment/37bb1a64_474da67b
PS2, Line 6: <fsp/util.h>
nit:
`<fsp/api.h>`
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Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/common: Retry END_OF_POST command
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Patch Set 12: Code-Review+1
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 12:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62192/comment/b57133aa_caa382d6
PS12, Line 15: TEST=Verify EOP retry mechanism for brya board.
> Let me rephrase: how many tries are actually needed on brya?
Only 1 try is required, we're just being thorough here.
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Patch Set 25: Code-Review+2
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Hello build bot (Jenkins), Cliff Huang, Selma Bensaid, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62654
to look at the new patch set (#11).
Change subject: soc/intel/alderlake: Add EPP override support
......................................................................
soc/intel/alderlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com>
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
2 files changed, 23 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/11
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