coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: set GPP_D0 to unlocked
by Zhuohao Lee (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: YH Lin, Nick Vaccaro, Mark Hsieh, EricR Lai, Felix Held. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 ) Change subject: mb/google/brya: set GPP_D0 to unlocked ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/62739/comment/7324938b_ff0d2ecd PS2, Line 122: /* D1 : ISH_GP1 ==> FP_RST_ODL */ : PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), : /* D2 : ISH_GP2 ==> EN_FP_PWR */ : PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), Does these two gpio also needs to be changed too? The flash_fp_mcu also uses these two pins -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Mar 2022 02:10:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Pass dram info to cbmem
by Hung-Te Lin (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Xi Chen, Paul Menzel, Xixi Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Pass dram info to cbmem ...................................................................... Patch Set 18: (6 comments) File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/c3c2e039_8c0149f1 PS18, Line 107: blob probably not 'blob'. what about 'ddr_info' or 'ddr'? https://review.coreboot.org/c/coreboot/+/61334/comment/5249c7b1_f299c0bb PS18, Line 106: struct mem_chip *p = &curr_dram_info; : const struct ddr_base_info *blob = curr_ddr_info; move these to the parameters and pass them from the caller? maybe rename like fill_dram_info() https://review.coreboot.org/c/coreboot/+/61334/comment/70f89f3d_78943cc7 PS18, Line 107: only one space https://review.coreboot.org/c/coreboot/+/61334/comment/fe2223dc_dcdedd50 PS18, Line 112: unsigned int i = 0 move to beginning of the function and declare only one time https://review.coreboot.org/c/coreboot/+/61334/comment/175cdb22_416f49ec PS18, Line 128: /* Add cbmem */ the cbmem_add is clear enough, no need to have this comment https://review.coreboot.org/c/coreboot/+/61334/comment/bdf480a0_04248a08 PS18, Line 130: + sizeof(curr_dram_info.channel) * CHANNEL_MAX) so we allocated more but won't copy the rest of them? (the memcpy only copies sizeof(curr_dram_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 18 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 02:07:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax...
by Curtis Chen (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Curtis Chen, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62727 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values ...................................................................... soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values Add ADL-P MCH ID 4, 8, 9, 10 into this list. BUG=b:222038287 BRANCH=firmware-brya-14505.B TEST=Build and check fsp log to confirm the settings are set properly. Signed-off-by: Curtis Chen <curtis.chen(a)intel.com> Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62727/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cee31ba56e0b142c50a745c453968635e86296e Gerrit-Change-Number: 62727 Gerrit-PatchSet: 2 Gerrit-Owner: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by John Zhao (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Patrick Rudolph. John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62721 ) Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/p2sb/ioe_p2sb.c: https://review.coreboot.org/c/coreboot/+/62721/comment/3a77fe11_504b7539 PS2, Line 56: .vendor = PCI_VENDOR_ID_INTEL, > Could you update to PCI_VID_INTEL? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 01:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add IOE P2SB for TCSS
by John Zhao (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, John Zhao, Tim Wawrzynczak, Patrick Rudolph. Hello build bot (Jenkins), Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62721 to look at the new patch set (#3). Change subject: soc/intel/common: Add IOE P2SB for TCSS ...................................................................... soc/intel/common: Add IOE P2SB for TCSS Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB sideband access and exposes API for TCSS usage. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h M src/soc/intel/common/block/p2sb/Kconfig M src/soc/intel/common/block/p2sb/Makefile.inc A src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c 5 files changed, 74 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62721/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19 Gerrit-Change-Number: 62721 Gerrit-PatchSet: 3 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down
by Rex-BC Chen (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Jianjun Wang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62673 ) Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: please also rebase this series. -- To view, visit https://review.coreboot.org/c/coreboot/+/62673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387 Gerrit-Change-Number: 62673 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 01:44:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: set GPP_D0 to unlocked
by Mark Hsieh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: YH Lin, Nick Vaccaro, Zhuohao Lee, EricR Lai, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 ) Change subject: mb/google/brya: set GPP_D0 to unlocked ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62739/comment/425c4c14_2bcef037 PS1, Line 10: GPPD0 > `GPP_D0` Updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Mar 2022 01:43:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down
by Rex-BC Chen (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Jianjun Wang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62673 ) Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62673/comment/2414ad6a_c9f5056f PS1, Line 13: BUG=b:178565024 -- To view, visit https://review.coreboot.org/c/coreboot/+/62673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387 Gerrit-Change-Number: 62673 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 01:43:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: set GPP_D0 to unlocked
by Mark Hsieh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: YH Lin, Nick Vaccaro, Mark Hsieh, Zhuohao Lee, EricR Lai, Felix Held. Hello build bot (Jenkins), YH Lin, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, EricR Lai, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62739 to look at the new patch set (#2). Change subject: mb/google/brya: set GPP_D0 to unlocked ...................................................................... mb/google/brya: set GPP_D0 to unlocked Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is directly connected to FP module, When GPP_D0 is locked, DUT cannot successfully flash FP firmware. BUG=b:222188263 TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint Firmware Test. Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/62739/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Fix null pointer dereference error when PCIe link down
by Jianjun Wang (Code Review) 11 Mar '22

11 Mar '22

Jianjun Wang has restored this change. ( https://review.coreboot.org/c/coreboot/+/62673 ) Change subject: soc/mediatek: Fix null pointer dereference error when PCIe link down ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/62673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ba1a47b58fc8fe6dd5cd22682cbc8de22ed2387 Gerrit-Change-Number: 62673 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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