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Change subject: mb/google/brya/var/kinox: Modify the DPTF/Fan parameters
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Hi Sumeet,
Could you help to review. Thank you.
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Change subject: amd/*/Makefile.inc: Put common words into common Makefile.inc
......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2:
https://review.coreboot.org/c/coreboot/+/62750
this CL can make sure the common is handled earlier.
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Change subject: amd/*/Makefile.inc: Put common words into common Makefile.inc
......................................................................
Patch Set 2: Code-Review-1
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62750
to review the following change.
Change subject: $(TOP)/Makefile.inc: Handle the folder common before specific one
......................................................................
$(TOP)/Makefile.inc: Handle the folder common before specific one
We can put some common variable in all the subdir Makefile.inc to the
common Makefile.inc to reduce the code duplication.
Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M Makefile.inc
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/62750/1
diff --git a/Makefile.inc b/Makefile.inc
index ec2d097..83607a2 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -81,7 +81,8 @@
# root source directories of coreboot
subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
-subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
+subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(wildcard src/soc/*/*)
+subdirs-y += $(wildcard src/northbridge/*/*)
subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*)
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
subdirs-y += src/cpu src/vendorcode
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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
Patch Set 13:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62192/comment/c2e7b1c6_5e50e35c
PS12, Line 11: max 3 times
> Well, your commit message says something different and even your comment is not consistent :P […]
Ack
https://review.coreboot.org/c/coreboot/+/62192/comment/bf996aad_2b098c67
PS12, Line 15: TEST=Verify EOP retry mechanism for brya board.
> > Let me rephrase: how many tries are actually needed on brya? […]
Ack
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Hello build bot (Jenkins), Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62192
to look at the new patch set (#13).
Change subject: soc/intel/common: Retry END_OF_POST command
......................................................................
soc/intel/common: Retry END_OF_POST command
As per ME BWG, the patch retries END_OF_POST command if CSE doesn't
respond or sends the garbled response. It retries the command
additionally 2 more times.
BUG=b:200251277
TEST=Verify EOP retry mechanism for brya board.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ieaec4d5564e3d962c1cc866351e9e7eaa8e58683
---
M src/soc/intel/common/block/cse/cse_eop.c
1 file changed, 33 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/62192/13
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Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
......................................................................
Patch Set 14:
(1 comment)
Patchset:
PS14:
Hi Karthik,
Could you please help review?
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Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62566/comment/d997dd0a_d10c9ece
PS2, Line 10: done by FSP
> Yes Subrata, sorry for being unprecise. […]
Done
https://review.coreboot.org/c/coreboot/+/62566/comment/26b48d8c_c4331227
PS2, Line 12: done by FSP
> Is this like FSP doing MP Init USE_INTEL_FSP_MP_INIT?
At least for me it is the hybrid MP init mode.
https://review.coreboot.org/c/coreboot/+/62566/comment/5031dd78_20105c35
PS2, Line 15: Now, in this scenario, the SPI
: flash linear address range is not registered as a resource (since the
: common SPI driver in src/soc/intel/common/block/spi is shared across
: multiple SPI controllers and therefore cannot distinguish where the
: flash is actually located at)
> > So you are referring to UFS, right? I am not familiar with UFS, I guess it is linear mapped into t […]
I guss reserving the flash region would be another patch. I will try to set one up.
https://review.coreboot.org/c/coreboot/+/62566/comment/2554268c_a2c88275
PS2, Line 19: uncached flash
: range
> The thing here is like described: Once coreboot MTRR setup is executed, the ranges are computed base […]
Ack
https://review.coreboot.org/c/coreboot/+/62566/comment/e8203c33_bcab6496
PS2, Line 20: The result of this chain is
: that loading the payload from flash takes much longer now (on mc_ehl1 it
: takes ~12 seconds for 4.5 MB).
> There is a chance that this is indeed platform related. […]
In the end the long delay only is visible if TPM_MEASURED_BOOT is selected. The reason for this is that the hash function gets the memory mapped flash region for hashing and performs the hashing in little chunks (since CB:59681). If now the flash region is not cached by the MTRR, this hashing will take way longer.
File src/soc/intel/common/block/cpu/mp_init.c:
https://review.coreboot.org/c/coreboot/+/62566/comment/81bc3fa1_24e0277e
PS2, Line 164: MP_SERVICES_PPI
> > I have access to one ADL-N RVP board, that shows some sluggishness in depthcharge. […]
So you tell me that with this patch your Alder Lake board has issues? I still do not see how it is is I2C TPM related...Is your TPM mapped into linear address space? And again, when do this issue start to appear, right after the call to 'mtrr_use_temp_range()'?
At least for Elkhart Lake I would love to have this patch as it saves me 8 seconds of boot time. Should I add a Kconfig switch for that so that this can be selected per platform then?
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