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Change in coreboot[master]: intel/block/cpu: Provide a way to cache the flash region temporary
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Lean Sheng Tan, Patrick Rudolph. Hello Arthur Heymans, build bot (Jenkins), Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Lean Sheng Tan, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62566 to look at the new patch set (#3). Change subject: intel/block/cpu: Provide a way to cache the flash region temporary ...................................................................... intel/block/cpu: Provide a way to cache the flash region temporary Since FSP version 2.1 EFI_MP_SERVICES_PPI can be used to bring up all the APs. For some SOCs it is mandatory that MP init is driven by FSP in order to have the full features enabled (e.g. Elkhart Lake or Alder Lake). In this mode FSP does the real MP init while coreboot provides some callbacks (hybrid mode). In this set up, early MTRR setup is done by FSP, too. Later in the boot flow, in BS_WRITE_TABLES exit, the MTRR setup is re-configured by coreboot native code based on the registered resources. This is done before payload is loaded. Now, in this scenario, the SPI flash linear address range is not registered as a resource (since the common SPI driver in src/soc/intel/common/block/spi is shared across multiple SPI controllers and therefore cannot distinguish where the flash is actually located at). This in turn leads to an uncached flash range when coreboot re-configures the MTRRs. The result of this chain is that loading the payload from flash with TPM_MEASURED_BOOT selected takes much longer now (on mc_ehl1 it takes ~12 seconds for 4.5 MB). This patch adds a Kconfig option to enable flash caching in this scenario, Once the switch is selected (which can be done on SOC level), a call to 'mtrr_use_temp_range()' right after the MTRR setup has been performed by coreboot ensures that the flash region is coverd by a MTRR. This MTRR setup is still tempirary and will be removed before payload is executed. But in turn, it speeds up payload loading a lot when TPM_MEASURED_BOOT is selected (on mc_ehl1 now to ~4 seconds). The call to 'mtrr_use_temp_range()' has to be done after MTRR setup as otherwise there will be no free variable MTRR slot available due to the missing initialization of the MTRR structure. Here is the timestamp snippet showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/mp_init.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62566/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: docs/contributing/gsoc: Add a collection of useful GSoC links
by Felix Singer (Code Review) 11 Mar '22

11 Mar '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62660 ) Change subject: docs/contributing/gsoc: Add a collection of useful GSoC links ...................................................................... docs/contributing/gsoc: Add a collection of useful GSoC links Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62660 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/contributing/gsoc.md 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/Documentation/contributing/gsoc.md b/Documentation/contributing/gsoc.md index bcc732a..ba94f20 100644 --- a/Documentation/contributing/gsoc.md +++ b/Documentation/contributing/gsoc.md @@ -33,6 +33,25 @@ framework for initial hardware initialization and you can help us succeed. +## Collection of official GSoC guides & documents + + * [Timeline][GSoC Timeline] + + * [Roles and Responsibilities][GSoC Roles and Responsibilities] + + * [Contributor Guide][GSoC Contributor Guide] + + * [Contributor Advice][GSoC Contributor Advice] + + * [Mentor Guide][GSoC Mentor Guide] + + * [FAQ][GSoC FAQ] + + * [Rules][GSoC Rules] + + * [Glossary][GSoC Glossary] + + ## Contributor requirements & commitments Google Summer of Code is a significant time commitment for you. Medium-sized @@ -245,5 +264,11 @@ [Coding style]: coding_style.md [Code of Conduct]: ../community/code_of_conduct.md [Language style]: ../community/language_style.md +[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline +[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities [GSoC Contributor Guide]: https://google.github.io/gsocguides/student +[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice [GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor +[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq +[GSoC Rules]: https://summerofcode.withgoogle.com/rules +[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary -- To view, visit https://review.coreboot.org/c/coreboot/+/62660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Gerrit-Change-Number: 62660 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: TEST WWAN VELL
by Robert Chen (Code Review) 11 Mar '22

11 Mar '22

Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62753 ) Change subject: TEST WWAN VELL ...................................................................... TEST WWAN VELL Change-Id: Ia5eb40f067365665f03a1884d1eb62b15a1a238d --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62753/1 diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 5f2780e..544062a 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -155,6 +155,28 @@ device generic 0 on end end end + device ref pcie_rp6 on + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)" + register "reset_off_delay_ms" = "20" + # register "reset_delay_ms" = "1000" + register "srcclk_pin" = "5" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp6_rtd3 on end + end + chip drivers/pcie/generic + register "is_untrusted" = "1" + use rp6_wwan as companion_dev + device pci 0 on end + end + end device ref pcie_rp8 off end device ref pcie_rp9 off end device ref tcss_dma0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/62753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5eb40f067365665f03a1884d1eb62b15a1a238d Gerrit-Change-Number: 62753 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/common: Add halt() after triggering wdt reset
by Rex-BC Chen (Code Review) 11 Mar '22

11 Mar '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62752 ) Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ...................................................................... soc/mediatek/common: Add halt() after triggering wdt reset It's more reasonable to halt when we trigger watchdog reset because whole system should be reset after we trigger watchdog reset. BUG=b:222217317 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb --- M src/soc/mediatek/common/wdt.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62752/1 diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 4f8eff2..b012011 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -3,11 +3,23 @@ #include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> +#include <halt.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h> __weak void mtk_wdt_clr_status(void) { /* do nothing */ } +static inline void mtk_wdt_swreset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + + dcache_clean_all(); + setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + halt(); +} + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -31,9 +43,7 @@ * Before triggering secondary reset, clean the data cache so the logs in cbmem * console (either in SRAM or DRAM) can be flushed. */ - dcache_clean_all(); - setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + mtk_wdt_swreset(); } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); else if (wdt_sta & MTK_WDT_STA_SPM_RST) -- To view, visit https://review.coreboot.org/c/coreboot/+/62752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Gerrit-Change-Number: 62752 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docs/contributing/gsoc: Add a collection of useful GSoC links
by Anastasia Klimchuk (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Felix Singer, Martin Roth, David Hendricks. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62660 ) Change subject: docs/contributing/gsoc: Add a collection of useful GSoC links ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Gerrit-Change-Number: 62660 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 08:55:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: docs/contributing/gsoc: Add a collection of useful GSoC links
by Felix Singer (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Martin Roth, David Hendricks, Anastasia Klimchuk. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62660 ) Change subject: docs/contributing/gsoc: Add a collection of useful GSoC links ...................................................................... Patch Set 5: (1 comment) File Documentation/contributing/gsoc.md: https://review.coreboot.org/c/coreboot/+/62660/comment/f4969cbd_5a26f22c PS3, Line 5: * [Timeline][GSoC Timeline] > Just to check, this is side-menu, and another diff below is bottom-menu? […] Yes, this also will be shown in the side-menu like this: * [...] * Collection of official GSoC guides & documents * Timeline * Roles and Responsibilities * [...] * [...] The sub-items (Timeline, Roles and Responsibilities, ...) don't contain a single character which isn't a link. In this case, the generator adds these points to the ToC tree. That's not intended by me, but I couldn't find a solution which doesn't add these points to the ToC tree. I will try to investigate that more later. -- To view, visit https://review.coreboot.org/c/coreboot/+/62660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Gerrit-Change-Number: 62660 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 08:51:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/cbfs: Enable payload mirroring into RAM
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62751 ) Change subject: lib/cbfs: Enable payload mirroring into RAM ...................................................................... lib/cbfs: Enable payload mirroring into RAM Since commit 7e7cc1a8c9a87e33bd772e8526734c7a82ec2db7 the measuring of the payload has been refactored with the assumption that access to a memory mapped flash region is comparably fast to a RAM region. This is not necessarily true for all platforms, especially when the flash region is not cached. On this platforms, measuring the payload can be very slow which will slow down the overall boot process a lot. For example, on Elkhart Lake loading and measuring a 4.5 MB payload with a 20 MHz single SPI interface takes ~12 seconds: 90:starting to load payload 1,133,387 (1,770) 958:calling FspNotify(ReadyToBoot) 12,879,028 (11,745,640) To speed this up mirroring the payload into DRAM can help a lot. The same mainboard with this patch applied needs just ~3.5 seconds to load the payload: 90:starting to load payload 1,119,405 (1,803) 958:calling FspNotify(ReadyToBoot) 4,661,876 (3,542,471) On a mainboard based on Apollo Lake (mc_apl5) this patch speeds up payload loading by ~1 seconds (1.5 sec without this patch, 0,6 with this patch applied): 90:load payload 2,119,183 (67) 958:calling FspNotify(ReadyToBoot) 3,635,886 (1,516,702) vs: 90:load payload 2,108,146 (68) 958:calling FspNotify(ReadyToBoot) 2,773,016 (664,869) Since mirroring the payload just improves the boot time when TPM_MEASURED_BOOT is enabled, the new introduced Kconfig switch can only be selected if TPM_MEASURED_BOOT is selected, too. Enabling it will load the payload into RAM before it is used. Change-Id: I94fc1a6d7c2543a7f1612314011dca47d29b79d0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M payloads/Kconfig M src/lib/cbfs.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/62751/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index 386b207..d0d0ee3 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -104,6 +104,14 @@ Enables FIT parser and devicetree patching. The FIT is non self-extracting and needs to have a compatible compression format. +config PAYLOAD_MIRROR_TO_RAM + def_bool n + depends on TPM_MEASURED_BOOT + help + When this option is selected, the payload will be mirrored into RAM + before it is being measured. Copying the payload to RAM can speed up the + boot process a lot. + config COMPRESS_SECONDARY_PAYLOAD bool "Use LZMA compression for secondary payloads" default y @@ -111,6 +119,7 @@ In order to reduce the size secondary payloads take up in the ROM chip they can be compressed using the LZMA algorithm. + menu "Secondary Payloads" config COREINFO_SECONDARY_PAYLOAD diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c8ca14c..4944e62 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -474,6 +474,17 @@ if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) preload_successful = true; + /* Mirror the payload to RAM to speed up booting. */ + if (CONFIG(PAYLOAD_MIRROR_TO_RAM) && ENV_RAMSTAGE && + !strcmp(name, CONFIG_CBFS_PREFIX "/payload")) { + size_t size = region_device_sz(&rdev); + void *buf = bootmem_allocate_buffer(size); + if (!buf || + rdev_read_full(&rdev, buf) != size || + rdev_chain_mem(&rdev, buf, size) != 0) + printk(BIOS_ERR, "Not able to mirror the payload to RAM\n"); + } + void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, false); /* When using cbfs_preload we need to free the preload buffer after populating the -- To view, visit https://review.coreboot.org/c/coreboot/+/62751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94fc1a6d7c2543a7f1612314011dca47d29b79d0 Gerrit-Change-Number: 62751 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: docs/contributing/gsoc: Add a collection of useful GSoC links
by Felix Singer (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Felix Singer, Martin Roth, David Hendricks. Hello build bot (Jenkins), Martin Roth, David Hendricks, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62660 to look at the new patch set (#5). Change subject: docs/contributing/gsoc: Add a collection of useful GSoC links ...................................................................... docs/contributing/gsoc: Add a collection of useful GSoC links Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/contributing/gsoc.md 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62660/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a1564f41d796ce86179d06b1d0b64021dc0a43 Gerrit-Change-Number: 62660 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: 9elements QA, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, 9elements QA, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#10). Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variables to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 41 files changed, 300 insertions(+), 290 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer. Hello build bot (Jenkins), Mario Scheithauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62698 to look at the new patch set (#3). Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62698/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022