coreboot-gerrit March 2022

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Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62698/comment/764c582a_4f11cd4c PS1, Line 7: Use 512 bytes for SPD buffer > Maybe: […] Sure, fine with me. https://review.coreboot.org/c/coreboot/+/62698/comment/8eb5d0ab_307784de PS1, Line 9: DDR4 SPD data needs to be 512 byte to comply with the spec. : Though there is no vital timing data used beyond 256 byte there are some : part information which will be used to show the part info in the : coreboot log. If the buffer is too small this log shows garbage. > Please add a blank line between paragraphs. Ack https://review.coreboot.org/c/coreboot/+/62698/comment/248b5e1a_338e98ca PS1, Line 13: > Maybe give an example line with garbled data? I do not use this part number hence cannot provide an example. File src/mainboard/siemens/mc_ehl/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/62698/comment/7c75d7f6_c0ebf033 PS1, Line 28: hexdump(spd_data, sizeof(spd_data)); > Is this debugging leftover? Ups, yes. This one slipped in, will remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/spd: Do not print part number if it is not available
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons, Arthur Heymans. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62699 ) Change subject: lib/spd: Do not print part number if it is not available ...................................................................... Patch Set 1: (1 comment) File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/62699/comment/6cfa7f67_5d62f0af PS1, Line 173: } > Print some placeholder as the part number? UNKNOWN or so? I would rather like to skip this line if there is no part number as there is no additional information that can be gained from an "UNKNOWN". -- To view, visit https://review.coreboot.org/c/coreboot/+/62699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Gerrit-Change-Number: 62699 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:52:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Hello build bot (Jenkins), Mario Scheithauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62698 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62698/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/spd: Do not print part number if it is not available
by Paul Menzel (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Subrata Banik, Angel Pons, Arthur Heymans, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62699 ) Change subject: lib/spd: Do not print part number if it is not available ...................................................................... Patch Set 1: (1 comment) File src/lib/spd_bin.c: https://review.coreboot.org/c/coreboot/+/62699/comment/e0c189bc_cda31b09 PS1, Line 173: } Print some placeholder as the part number? UNKNOWN or so? -- To view, visit https://review.coreboot.org/c/coreboot/+/62699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Gerrit-Change-Number: 62699 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:37:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Use 512 bytes for SPD buffer
by Paul Menzel (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Use 512 bytes for SPD buffer ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62698/comment/b883869b_e798c751 PS1, Line 7: Use 512 bytes for SPD buffer Maybe: > Double SPD buffer size to 512 bytes https://review.coreboot.org/c/coreboot/+/62698/comment/99cf87c6_6e8bc3b0 PS1, Line 9: DDR4 SPD data needs to be 512 byte to comply with the spec. : Though there is no vital timing data used beyond 256 byte there are some : part information which will be used to show the part info in the : coreboot log. If the buffer is too small this log shows garbage. Please add a blank line between paragraphs. https://review.coreboot.org/c/coreboot/+/62698/comment/58e36fe2_043681ea PS1, Line 13: Maybe give an example line with garbled data? File src/mainboard/siemens/mc_ehl/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/62698/comment/0ecc486e_016377a7 PS1, Line 28: hexdump(spd_data, sizeof(spd_data)); Is this debugging leftover? -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:36:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/wifi/generic: Add ops to generic cnvi device
by Paul Menzel (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62746 ) Change subject: drivers/wifi/generic: Add ops to generic cnvi device ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62746/comment/2c05c86e_482ca03d PS1, Line 16: TEST=error message about a GENERIC 0.0 device missing read_resources is : gone. On what device? -- To view, visit https://review.coreboot.org/c/coreboot/+/62746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafd86458d2f65ccb7e74d1308d37fd3ebbf7f520 Gerrit-Change-Number: 62746 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:33:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC power control setting
by Dtrain Hsu (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Nick Vaccaro, Felix Held, Zhuohao Lee. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62627 ) Change subject: mb/google/brya/var/kinox: Modify 15W SOC power control setting ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Sorry for update CL again. Get a request for update Psys_PL2, Psys_imax_ma, bj_volts_mv from https://partnerissuetracker.corp.google.com/issues/222599762#comment15. -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 5 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:28:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: 9elements QA, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62645 ) Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Sorry +2 again went due to upstream merge conflicts. -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 11 Mar 2022 07:27:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Maulik V Vaghela (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Maulik V Vaghela, Patrick Rudolph. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62645 to look at the new patch set (#9). Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... soc/intel/adl/chip.h: Convert all camel case variables to snake case coreboot chip.h files mainly contains variable which allows board to fill platform configuration through devicetree. Since many of this configuration involves FSP UPDs, variable names were in camel case which aligned with UPD naming convention. By default coreboot follow snake case variable naming, so cleaning up file to align all variable names as per coreboot convention. During renaming process, this patch also removes unused variables listed below: -> SataEnable // Checked in SoC code based on PCI dev enabled status -> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used Note: Since separating out changes into smaller CL might break the compilation for the patch set, this is being pushed as a single big CL. BUG=None BRANCH=firmware-brya-14505.B TEST=All boards using ADL SoC compiles with the CL. Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/google/brya/variants/agah/overridetree.cb M src/mainboard/google/brya/variants/anahera/overridetree.cb M src/mainboard/google/brya/variants/anahera4es/overridetree.cb M src/mainboard/google/brya/variants/banshee/overridetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/ramstage.c M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/brask/variant.c M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya0/variant.c M src/mainboard/google/brya/variants/brya4es/overridetree.cb M src/mainboard/google/brya/variants/brya4es/variant.c M src/mainboard/google/brya/variants/felwinter/overridetree.cb M src/mainboard/google/brya/variants/felwinter/variant.c M src/mainboard/google/brya/variants/gimble/overridetree.cb M src/mainboard/google/brya/variants/gimble/variant.c M src/mainboard/google/brya/variants/gimble4es/overridetree.cb M src/mainboard/google/brya/variants/gimble4es/variant.c M src/mainboard/google/brya/variants/kano/overridetree.cb M src/mainboard/google/brya/variants/kano/variant.c M src/mainboard/google/brya/variants/nereid/overridetree.cb M src/mainboard/google/brya/variants/nivviks/overridetree.cb M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb M src/mainboard/google/brya/variants/taeko/overridetree.cb M src/mainboard/google/brya/variants/taeko4es/overridetree.cb M src/mainboard/google/brya/variants/taniks/overridetree.cb M src/mainboard/google/brya/variants/vell/overridetree.cb M src/mainboard/google/brya/variants/volmar/overridetree.cb M src/mainboard/google/brya/variants/volmar/variant.c M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/prodrive/atlas/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 41 files changed, 295 insertions(+), 285 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62645/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 9 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/kinox: Modify 15W SOC power control setting
by Dtrain Hsu (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Nick Vaccaro, Felix Held, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62627 to look at the new patch set (#5). Change subject: mb/google/brya/var/kinox: Modify 15W SOC power control setting ...................................................................... mb/google/brya/var/kinox: Modify 15W SOC power control setting Modify 15W SOC default power settings for kinox. - PL2 39W - PL4 100W - Psys_PL2 65W - Psys_imax_ma 5000ma - bj_volts_mv 20000mv BUG=b:213417026, b:222599762 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 --- M src/mainboard/google/brya/variants/kinox/Makefile.inc A src/mainboard/google/brya/variants/kinox/ramstage.c 2 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/62627/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2956705f7d26929c7cf2dd4e852fc61b619a83e5 Gerrit-Change-Number: 62627 Gerrit-PatchSet: 5 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022