coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: mb/google/brya: set GPP_D0 to unlocked
by Mark Hsieh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: YH Lin, Subrata Banik, Nick Vaccaro, Zhuohao Lee, EricR Lai, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 ) Change subject: mb/google/brya: set GPP_D0 to unlocked ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62739/comment/07d127f8_9e232630 PS1, Line 9: the GDD_D0 is : directly connected to FP module > if this is connected to SoC, then why we have configured as PAD_NC. […] Set GPP_D0 to PAD_CFG_GPO File src/mainboard/google/brya/variants/baseboard/brya/gpio.c: https://review.coreboot.org/c/coreboot/+/62739/comment/17ffeea6_f7e2abbe PS2, Line 122: /* D1 : ISH_GP1 ==> FP_RST_ODL */ : PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), : /* D2 : ISH_GP2 ==> EN_FP_PWR */ : PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), > Does these two gpio also needs to be changed too? The flash_fp_mcu also uses these two pins Hi Zhuohao, When unlocked GPP_D0,GPP_D1 and GPP_D2,DUT cannot record fingerprint. But only unlocked GPP_D0, DUT can record fingerprint successfully -- To view, visit https://review.coreboot.org/c/coreboot/+/62739 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5 Gerrit-Change-Number: 62739 Gerrit-PatchSet: 3 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Mar 2022 14:30:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib/spd: Do not print part number if it is not available
by Subrata Banik (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Angel Pons, Arthur Heymans, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62699 ) Change subject: lib/spd: Do not print part number if it is not available ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62699/comment/da4cb05d_a0d05b3f PS4, Line 11: Can we please capture the output in the commit msg as well? (incase spd[DDR4_SPD_PART_OFF] == 0), will it display "unknown"? -- To view, visit https://review.coreboot.org/c/coreboot/+/62699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7224c6e114731b1c03915a2bde80f57369d0cee Gerrit-Change-Number: 62699 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 14:06:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: $(TOP)/Makefile.inc: Handle the folder common before specific one
by Bao Zheng (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Elyes Haouas, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62750 ) Change subject: $(TOP)/Makefile.inc: Handle the folder common before specific one ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62750/comment/0d9747b4_d94cedef PS1, Line 9: variable variables -- To view, visit https://review.coreboot.org/c/coreboot/+/62750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Gerrit-Change-Number: 62750 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 11 Mar 2022 13:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Angel Pons (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Damien Zammit. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... Patch Set 1: Code-Review+1 (5 comments) File src/mainboard/hp/z220_sff_workstation/Kconfig: https://review.coreboot.org/c/coreboot/+/62759/comment/c9c16218_f98e225e PS1, Line 1: BOARD_HP_Z220_VARIANT As this symbol is for a group of boards, I'd rename it to `BOARD_HP_Z220_SERIES` https://review.coreboot.org/c/coreboot/+/62759/comment/4ef7308b_31fa64c6 PS1, Line 52: Please don't make a copy of data.vbt, just keep it where it is and add this here: # Override the default variant behavior, since the data.vbt is the same config INTEL_GMA_VBT_FILE default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" https://review.coreboot.org/c/coreboot/+/62759/comment/723cc542_8c56df18 PS1, Line 53: config VGA_BIOS_FILE : string : default "pci8086,0102.rom" : : config VGA_BIOS_ID : string : default "8086,0102" Where did this come from? Please remove, it doesn't make sense for a board with a socketed CPU. File src/mainboard/hp/z220_sff_workstation/Kconfig.name: https://review.coreboot.org/c/coreboot/+/62759/comment/5a01c65b_06fd00a6 PS1, Line 3: nit: spaces not needed File src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c: PS1: Are there many differences between the GPIO settings? -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Fri, 11 Mar 2022 12:58:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Documentation: Use file paths to flashing firmware tutorial
by Angel Pons (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Felix Singer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62452 ) Change subject: Documentation: Use file paths to flashing firmware tutorial ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a271a912348cbe002bc9cced9922ed743e1133c Gerrit-Change-Number: 62452 Gerrit-PatchSet: 9 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 11 Mar 2022 12:46:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Angel Pons (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... Patch Set 4: (1 comment) File src/mainboard/siemens/mc_ehl/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/62698/comment/d0a349dc_af5a6c3f PS3, Line 17: 0x200 > Oh yes, will change. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 12:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Angel Pons (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Werner Zeh. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 12:28:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Angel Pons. Hello build bot (Jenkins), Mario Scheithauer, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62698 to look at the new patch set (#4). Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/62698/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 4 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Werner Zeh (Code Review) 11 Mar '22

11 Mar '22

Attention is currently required from: Paul Menzel, Mario Scheithauer, Angel Pons. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/siemens/mc_ehl/romstage_fsp_params.c: https://review.coreboot.org/c/coreboot/+/62698/comment/1b65eee6_d6b02a26 PS3, Line 17: 0x200 > How about `CONFIG_DIMM_SPD_SIZE` instead? Oh yes, will change. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Mar 2022 11:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Damien Zammit (Code Review) 11 Mar '22

11 Mar '22

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... hp/z220_cmt_workstation: Add variant of z220_sff_workstation This is based on work done by a good friend of mine. The code in this commit is untested as I reworked his port into a variant. We will be testing it on the CMT soon. Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig.name M src/mainboard/hp/z220_sff_workstation/Makefile.inc M src/mainboard/hp/z220_sff_workstation/devicetree.cb C src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt A src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c A src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb R src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt R src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c A src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb 10 files changed, 252 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62759/1 diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index d706665..492d2a9 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -1,7 +1,6 @@ -if BOARD_HP_Z220_SFF_WORKSTATION +config BOARD_HP_Z220_VARIANT + def_bool n -config BOARD_SPECIFIC_OPTIONS - def_bool y select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,6 +19,8 @@ select GFX_GMA_ANALOG_I2C_HDMI_B select MAINBOARD_USES_IFD_GBE_REGION +if BOARD_HP_Z220_VARIANT + config VBOOT select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT @@ -38,8 +39,24 @@ config MAINBOARD_DIR default "hp/z220_sff_workstation" +config VARIANT_DIR + default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION + config MAINBOARD_PART_NUMBER - default "HP Z220 SFF Workstation" + default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VGA_BIOS_FILE + string + default "pci8086,0102.rom" + +config VGA_BIOS_ID + string + default "8086,0102" config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig.name b/src/mainboard/hp/z220_sff_workstation/Kconfig.name index 037ebc0..29515aa 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig.name +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig.name @@ -1,2 +1,10 @@ config BOARD_HP_Z220_SFF_WORKSTATION bool "Z220 SFF Workstation" + + select BOARD_HP_Z220_VARIANT + + +config BOARD_HP_Z220_CMT_WORKSTATION + bool "Z220 CMT Workstation" + + select BOARD_HP_Z220_VARIANT diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index f0b34f9..00426a8 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,5 +1,5 @@ -bootblock-y += gpio.c -romstage-y += gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 0de9cfa..4611bec 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -30,7 +30,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt similarity index 100% copy from src/mainboard/hp/z220_sff_workstation/data.vbt copy to src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c new file mode 100644 index 0000000..fb80217 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb new file mode 100644 index 0000000..0200e4d --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb @@ -0,0 +1,36 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 PCH + + register "sata_port_map" = "0x3f" + + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.5 on end # PCIe Port #6 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.4 on # LED control + io 0x60 = 0xa00 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0xa10 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + end + end + end + end + end + end +end diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/data.vbt rename to src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/gpio.c rename to src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb new file mode 100644 index 0000000..2b36363 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb @@ -0,0 +1,8 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0xf" + device pci 1c.4 on end # dummy setting + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022