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Change subject: soc/amd/common/block: Add mainboard_handle_smi
......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2:
Sorry, this one is ok to land
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Change subject: soc/amd/common/block: Add mainboard_handle_smi
......................................................................
Patch Set 2: Code-Review-1
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/62723/comment/d8ab8aef_f5ccb2f8
PS3, Line 389: else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) {
: if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB))
> Yes, I am working on future platform beyond the MTL which falls into 'else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) {' scope with the following implementation.
> ....
> else if (CONFIG(SOC_INTEL_COMMON_BLOCK_XYZ_P2SB))
> xyz_tcss_configure_aux_bias_pads_sbi(pads);
> ....
Sure, then leave this code as is.
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/tcss/tcss.c:
https://review.coreboot.org/c/coreboot/+/62723/comment/68326d46_1d71cc7b
PS3, Line 389: else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) {
: if (CONFIG(SOC_INTEL_COMMON_BLOCK_IOE_P2SB))
> > It seems the current format to be more descriptive to differentiate the _REGBAR and _SBI. […]
Yes, I am working on future platform beyond the MTL which falls into 'else if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI)) {' scope with the following implementation.
....
else if (CONFIG(SOC_INTEL_COMMON_BLOCK_XYZ_P2SB))
xyz_tcss_configure_aux_bias_pads_sbi(pads);
....
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62138 )
Change subject: apollolake mainboards: Set PMC as hidden in devicetree
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> > > Looks like the usual difference between APL/GLK and PCH platforms.
> >
> > Yup. Looking for suggestion, if a __weak implementation can be allowed here to land `pmc_clear_pmcon_sts()` in common for have overrides in APL SoC alone.
>
> What I mean is that the common implementation should be put into `src/soc/intel/common/pch/`, then we wouldn't need a weak symbol.
Just having pmc_clear_pmcon_sts() function alone into `src/soc/intel/common/pch/` won't make any sense. Also, moving the `pmc` block code into `src/soc/intel/common/pch/` is not scalable as APL/GLK/DNV also using this common PMC block.
WDYT? _weak implementation for pmc_clear_pmcon_sts() is the easiest option here ?
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Raul Rangel has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/62793 )
Change subject: cpu/x86/smm: Add smm_get_cbmemc_buffer for legacy SMI handler
......................................................................
cpu/x86/smm: Add smm_get_cbmemc_buffer for legacy SMI handler
Fixes the following error when using the legacy SMI handler:
> coreboot/util/crossgcc/xgcc/bin/i386-elf-ld.bfd: build/smm/smm.o: in function `cbmemc_init':
> coreboot/src/lib/cbmem_console.c:91: undefined reference to `smm_get_cbmemc_buffer'
BUG=b:221231786
TEST=none
Fixes: c5160986cf9 ("cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI")
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I3ba4952d2d2a984adaf8fe3508e6b82d396aa9bb
---
M src/cpu/x86/smm/smihandler.c
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62793/2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62784 )
Change subject: drivers/wifi/generic: Fix is_cnvi function
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I don't have any issues booting my brya0 with the code as-is (without this CL)...
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