coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 14 Mar '22

14 Mar '22

Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 21: (2 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/4067ba90_90411abe PS21, Line 243: mtk_pcie_get_hw_info > Every patch should be self-contained, so we should declare it in this patch. Done https://review.coreboot.org/c/coreboot/+/56791/comment/2ef40dec_2339d9bf PS21, Line 248: dev->chip_info = &pcie_ctrl; > Also, I don't think we should set chip_info in the code. It should be set in devicetree.cb instead. […] Done, please reference to these links: https://review.coreboot.org/c/coreboot/+/62791/2 https://review.coreboot.org/c/coreboot/+/62360/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 21 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 13:09:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Add LabTop Mk III
by Sean Rhodes (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58538 to look at the new patch set (#66). Change subject: mb/starlabs/labtop: Add LabTop Mk III ...................................................................... mb/starlabs/labtop: Add LabTop Mk III Tested using MrChromeBox's `uefipayload_202107` branch: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/labtop-mk-iii-specification Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/labtop_kbl.md M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/starlabs/labtop/Kconfig.name A src/mainboard/starlabs/labtop/acpi/ec.asl A src/mainboard/starlabs/labtop/acpi/superio.asl M src/mainboard/starlabs/labtop/dsdt.asl A src/mainboard/starlabs/labtop/variants/kbl/Makefile.inc A src/mainboard/starlabs/labtop/variants/kbl/board.fmd A src/mainboard/starlabs/labtop/variants/kbl/data.vbt A src/mainboard/starlabs/labtop/variants/kbl/devicetree.cb A src/mainboard/starlabs/labtop/variants/kbl/devtree.c A src/mainboard/starlabs/labtop/variants/kbl/gma-mainboard.ads A src/mainboard/starlabs/labtop/variants/kbl/gpio.c A src/mainboard/starlabs/labtop/variants/kbl/hda_verb.c A src/mainboard/starlabs/labtop/variants/kbl/romstage.c 16 files changed, 959 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/58538/66 -- To view, visit https://review.coreboot.org/c/coreboot/+/58538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36 Gerrit-Change-Number: 58538 Gerrit-PatchSet: 66 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe controller data
by Jianjun Wang (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62791 to look at the new patch set (#2). Change subject: soc/mediatek: Add chip config for setting PCIe controller data ...................................................................... soc/mediatek: Add chip config for setting PCIe controller data Add chip config for setting PCIe controller data. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c A src/soc/mediatek/mt8195/chip.h M src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/include/soc/soc_chip.h M src/soc/mediatek/mt8195/pcie.c 6 files changed, 78 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62791/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 2 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe controller data
by Jianjun Wang (Code Review) 14 Mar '22

14 Mar '22

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62791 ) Change subject: soc/mediatek: Add chip config for setting PCIe controller data ...................................................................... soc/mediatek: Add chip config for setting PCIe controller data Add chip config for setting PCIe controller data. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c A src/soc/mediatek/mt8195/chip.h M src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/include/soc/soc_chip.h M src/soc/mediatek/mt8195/pcie.c 6 files changed, 80 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62791/1 diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index d737c9d..fb74b11 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -15,10 +15,8 @@ struct mtk_pcie_controller { uintptr_t base; /* MAC physical address */ - int (*phy_init)(void); - void (*reset)(uintptr_t base, bool enable); - const struct mtk_pcie_mmio_res *mmio_res_io; - const struct mtk_pcie_mmio_res *mmio_res_mem; + const struct mtk_pcie_mmio_res mmio_res_io; + const struct mtk_pcie_mmio_res mmio_res_mem; }; void mtk_pcie_domain_read_resources(struct device *dev); diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c05db8c..068c58e 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -13,6 +13,7 @@ #include <soc/addressmap.h> #include <soc/pcie.h> #include <soc/pcie_common.h> +#include <soc/soc_chip.h> #include <stdlib.h> #include <types.h> @@ -64,7 +65,7 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -static struct mtk_pcie_controller pcie_ctrl; +static struct mtk_pcie_controller *pcie_ctrl; /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ static const char *const ltssm_str[] = { @@ -105,56 +106,9 @@ bus = PCI_DEV2SEGBUS(dev); val = PCIE_CFG_HEADER(bus, devfn); - write32p(pcie_ctrl.base + PCIE_CFGNUM_REG, val); + write32p(pcie_ctrl->base + PCIE_CFGNUM_REG, val); - return (void *)(pcie_ctrl.base + PCIE_CFG_OFFSET_ADDR); -} - -static int mtk_pcie_startup_port(struct mtk_pcie_controller *ctrl) -{ - uint32_t val; - size_t tries = 0; - const char *ltssm_state; - - /* Set as RC mode */ - val = read32p(ctrl->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(ctrl->base + PCIE_SETTING_REG, val); - - /* Set class code */ - val = read32p(ctrl->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(ctrl->base + PCIE_PCI_IDS_1, val); - - /* Mask all INTx interrupts */ - val = read32p(ctrl->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(ctrl->base + PCIE_INT_ENABLE_REG, val); - - if (!ctrl->reset) { - printk(BIOS_ERR, "%s: Missing reset function\n", __func__); - return -1; - } - - /* De-assert reset signals */ - ctrl->reset(ctrl->base + PCIE_RST_CTRL_REG, false); - - if (!retry(100, - (tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) & - PCIE_CTRL_LINKUP), mdelay(1))) { - val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG); - ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? - "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; - printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", - __func__, ltssm_state); - return -1; - } - - printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, - tries); - - return 0; + return (void *)(pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR); } static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, @@ -210,29 +164,35 @@ void mtk_pcie_domain_read_resources(struct device *dev) { - struct mtk_pcie_controller *ctrl = dev->chip_info; + const mtk_soc_config_t *config = config_of(dev); + struct mtk_pcie_controller *ctrl; + + ctrl = (struct mtk_pcie_controller *)&config->pcie_controller; mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0), - ctrl->mmio_res_io); + &ctrl->mmio_res_io); mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0), - ctrl->mmio_res_mem); + &ctrl->mmio_res_mem); } void mtk_pcie_domain_set_resources(struct device *dev) { - struct mtk_pcie_controller *ctrl = dev->chip_info; + const mtk_soc_config_t *config = config_of(dev); + struct mtk_pcie_controller *ctrl; uintptr_t table; + ctrl = (struct mtk_pcie_controller *)&config->pcie_controller; + /* Initialize I/O space constraints. */ table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_io) < 0) + if (mtk_pcie_set_trans_window(dev, table, &ctrl->mmio_res_io) < 0) printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__); /* Initialize memory resources constraints. */ table = ctrl->base + PCIE_TRANS_TABLE_BASE_REG + PCIE_ATR_TLB_SET_OFFSET; - if (mtk_pcie_set_trans_window(dev, table, ctrl->mmio_res_mem) < 0) + if (mtk_pcie_set_trans_window(dev, table, &ctrl->mmio_res_mem) < 0) printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__); pci_domain_set_resources(dev); @@ -240,10 +200,43 @@ void mtk_pcie_domain_enable(struct device *dev) { - mtk_pcie_get_hw_info(&pcie_ctrl); + const mtk_soc_config_t *config = config_of(dev); + const char *ltssm_state; + size_t tries = 0; + uint32_t val; - if (mtk_pcie_startup_port(&pcie_ctrl) < 0) + pcie_ctrl = (struct mtk_pcie_controller *)&config->pcie_controller; + + /* Set as RC mode */ + val = read32p(pcie_ctrl->base + PCIE_SETTING_REG); + val |= PCIE_RC_MODE; + write32p(pcie_ctrl->base + PCIE_SETTING_REG, val); + + /* Set class code */ + val = read32p(pcie_ctrl->base + PCIE_PCI_IDS_1); + val &= ~GENMASK(31, 8); + val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); + write32p(pcie_ctrl->base + PCIE_PCI_IDS_1, val); + + /* Mask all INTx interrupts */ + val = read32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG); + val &= ~PCIE_INTX_ENABLE; + write32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG, val); + + /* De-assert reset signals */ + mtk_pcie_reset(pcie_ctrl->base + PCIE_RST_CTRL_REG, false); + + if (!retry(100, + (tries++, read32p(pcie_ctrl->base + PCIE_LINK_STATUS_REG) & + PCIE_CTRL_LINKUP), mdelay(1))) { + val = read32p(pcie_ctrl->base + PCIE_LTSSM_STATUS_REG); + ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? + "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; + printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", + __func__, ltssm_state); return; + } - dev->chip_info = &pcie_ctrl; + printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, + tries); } diff --git a/src/soc/mediatek/mt8195/chip.h b/src/soc/mediatek/mt8195/chip.h new file mode 100644 index 0000000..f840c10 --- /dev/null +++ b/src/soc/mediatek/mt8195/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_CHIP_H +#define SOC_MEDIATEK_CHIP_H + +#include <device/device.h> +#include <types.h> +#include <soc/pcie_common.h> + +struct soc_mediatek_mt8195_config { + struct mtk_pcie_controller pcie_controller; +}; + +typedef struct soc_mediatek_mt8195_config mtk_soc_config_t; + +#endif /* SOC_MEDIATEK_CHIP_H */ diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 0978531..21a6668 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -5,7 +5,7 @@ #include <soc/pcie_common.h> +void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void); -void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl); #endif diff --git a/src/soc/mediatek/mt8195/include/soc/soc_chip.h b/src/soc/mediatek/mt8195/include/soc/soc_chip.h new file mode 100644 index 0000000..6b3c354 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/soc_chip.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_SOC_CHIP_H +#define SOC_MEDIATEK_SOC_CHIP_H + +#include "../../chip.h" + +#endif /* SOC_MEDIATEK_SOC_CHIP_H */ diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 8a1fca4..1a17c6c 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -19,23 +19,6 @@ #define PCIE_BRG_RSTB BIT(2) #define PCIE_PE_RSTB BIT(3) - -/* MMIO range (64MB): 0x20000000 ~ 0x24000000 */ -/* Some devices still need io ranges, reserve 16MB for compatibility */ -static const struct mtk_pcie_mmio_res pcie_mmio_res_io = { - .cpu_addr = 0x20000000, - .pci_addr = 0x20000000, - .size = 16 * MiB, - .type = IORESOURCE_IO, -}; - -static const struct mtk_pcie_mmio_res pcie_mmio_res_mem = { - .cpu_addr = 0x21000000, - .pci_addr = 0x21000000, - .size = 48 * MiB, - .type = IORESOURCE_MEM, -}; - struct pad_func { gpio_t gpio; u8 func; @@ -67,7 +50,7 @@ } } -static void mtk_pcie_reset(uintptr_t reg, bool enable) +void mtk_pcie_reset(uintptr_t reg, bool enable) { uint32_t val; @@ -90,11 +73,3 @@ /* Assert all reset signals at early stage */ mtk_pcie_reset(PCIE_RST_CTRL_REG, true); } - -void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl) -{ - ctrl->base = PCIE_REG_BASE_PORT0; - ctrl->mmio_res_io = &pcie_mmio_res_io; - ctrl->mmio_res_mem = &pcie_mmio_res_mem; - ctrl->reset = &mtk_pcie_reset; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Jianjun Wang (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62360 to look at the new patch set (#13). Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... mb/google/cherry: Add PCIe domain support Add override device tree for dojo and add PCIe domain support. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 --- M src/mainboard/google/cherry/Kconfig A src/mainboard/google/cherry/variants/dojo/overridetree.cb 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update APU STT setting
by Rob Barnes (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Kevin Chiu, Bhanu Prakash Maiya, Eric Peers, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62790 ) Change subject: mb/google/guybrush/var/nipperkin: update APU STT setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Gerrit-Change-Number: 62790 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 14 Mar 2022 12:37:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update APU STT setting
by Kevin Chiu (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Felix Held. Hello Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62790 to look at the new patch set (#2). Change subject: mb/google/guybrush/var/nipperkin: update APU STT setting ...................................................................... mb/google/guybrush/var/nipperkin: update APU STT setting BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/62790/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Gerrit-Change-Number: 62790 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update APU STT setting
by Kevin Chiu (Code Review) 14 Mar '22

14 Mar '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62790 ) Change subject: mb/google/guybrush/var/nipperkin: update APU STT setting ...................................................................... mb/google/guybrush/var/nipperkin: update APU STT setting BUG=b:219616787 BRANCH=guybrush TEST=emerge-guybrush coreboot update the thermal setting value by measurement and pass the thermal performance test Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/62790/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index adde71f..668c109 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -216,13 +216,13 @@ register "stt_control" = "1" register "stt_pcb_sensor_count" = "2" register "stt_min_limit" = "12000" - register "stt_m1" = "0x466" - register "stt_m2" = "0xFF3B" + register "stt_m1" = "0x04DE" + register "stt_m2" = "0x13" register "stt_m3" = "0" register "stt_m4" = "0" register "stt_m5" = "0" register "stt_m6" = "0" - register "stt_c_apu" = "0x14DA" + register "stt_c_apu" = "0xDA43" register "stt_c_gpu" = "0" register "stt_c_hs2" = "0" register "stt_alpha_apu" = "0x199A" -- To view, visit https://review.coreboot.org/c/coreboot/+/62790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45 Gerrit-Change-Number: 62790 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/chromeec: add fan speed rpm control
by Sumeet R Pawnikar (Code Review) 14 Mar '22

14 Mar '22

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62789 ) Change subject: ec/google/chromeec: add fan speed rpm control ...................................................................... ec/google/chromeec: add fan speed rpm control Add fan speed rpm control for DPTF based Active2 policy. BUG=b:224457192 BRANCH=None TEST=Built and booted on ADL-P based Brya system Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/ec/google/chromeec/acpi/ec.asl M src/ec/google/chromeec/ec_dptf_helpers.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/62789/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 69d608b..afb2293 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -82,6 +82,7 @@ BTID, 8, // Battery index that host wants to read USPP, 8, // USB Port Power RFWU, 8, // Retimer Firmware Update + CFSP, 8, // Set Fan speed in rpm } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) diff --git a/src/ec/google/chromeec/ec_dptf_helpers.c b/src/ec/google/chromeec/ec_dptf_helpers.c index 94b13fb..e54a034 100644 --- a/src/ec/google/chromeec/ec_dptf_helpers.c +++ b/src/ec/google/chromeec/ec_dptf_helpers.c @@ -109,6 +109,12 @@ acpigen_emit_namestring("TFST"); acpigen_write_integer(1); acpigen_emit_byte(ZERO_OP); /* 3rd arg to Index */ + acpigen_write_store(); + acpigen_emit_namestring(acpi_device_path_join(ec, "CFSP")); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring("TFST"); + acpigen_write_integer(2); + acpigen_emit_byte(ZERO_OP); acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring("TFST"); acpigen_pop_len(); /* Method _FST */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Gerrit-Change-Number: 62789 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/block: Add APL and GLK PCI IDs for HDA
by Sean Rhodes (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Sean Rhodes, Patrick Rudolph. Hello build bot (Jenkins), Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61804 to look at the new patch set (#5). Change subject: intel/common/block: Add APL and GLK PCI IDs for HDA ...................................................................... intel/common/block: Add APL and GLK PCI IDs for HDA Add PCI ID's for APL/GLK so they can use HDA. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 --- M src/soc/intel/common/block/hda/hda.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/61804/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 Gerrit-Change-Number: 61804 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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