coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62571 ) Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices ...................................................................... mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices GFX HDA is the audio controller that provides audio output via the external display connection, ACP is the audio coporcessor for the on- board audio codec and XHCI2 is the third XHCI controller that provides one USB 2.0 port. All those devices are used, so enable them in the board's devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/chausie/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Fred Reitberger: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 1d4d9da..f3a84f3 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -36,6 +36,7 @@ device ref gpp_bridge_5 on end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) + device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) device ref crypto on end # Crypto Coprocessor device ref xhci_0 on # USB 3.1 (USB0) chip drivers/usb/acpi @@ -73,6 +74,19 @@ end end end + device ref acp on end # Audio Processor (ACP) + end + device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C + device ref xhci_2 on + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_2_root_hub on + chip drivers/usb/acpi + device usb 2.0 alias usb2_port5 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/62571 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398 Gerrit-Change-Number: 62571 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62722 ) Change subject: mb/google/nissa/var/nivviks: Hook up SD host controller GL9750 ...................................................................... mb/google/nissa/var/nivviks: Hook up SD host controller GL9750 Select GL9750 driver and add power sequence according to datasheet: GL9750S-OIY04 rev1.22. BUG=b:223304292 TEST=check GL9750 can get enumerated by kernel 5.15. 01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01) Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/nivviks/gpio.c 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Reka Norman: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 186ca6f..9bf50ae 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -84,6 +84,7 @@ bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c index f0700ab..a5f9cb8 100644 --- a/src/mainboard/google/brya/variants/nivviks/gpio.c +++ b/src/mainboard/google/brya/variants/nivviks/gpio.c @@ -31,6 +31,8 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ @@ -45,6 +47,13 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) @@ -58,3 +67,10 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } + + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/62722 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d Gerrit-Change-Number: 62722 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/nissa/var/nivviks: Enable pen garage
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62675 ) Change subject: mb/google/nissa/var/nivviks: Enable pen garage ...................................................................... mb/google/nissa/var/nivviks: Enable pen garage Enable pen garage. Pen detect is active low. And wake system when eject. BUG=b:223476974 TEST=evtest work as expected. Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 0 Properties: Testing ... (interrupt to exit) Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Event: -------------- SYN_REPORT ------------ Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c M src/mainboard/google/brya/variants/nivviks/overridetree.cb 3 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 3895aab..186ca6f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -83,6 +83,7 @@ config BOARD_GOOGLE_NIVVIKS bool "-> Nivviks" select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_INTEL_MIPI_CAMERA select HAVE_WWAN_POWER_SEQUENCE diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 8a3ea0e..60b0018 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -238,7 +238,7 @@ /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI(GPP_F15, NONE, DEEP, EDGE_SINGLE, NONE), + PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, DEEP, EDGE_SINGLE), /* F16 : NC */ PAD_NC(GPP_F16, NONE), /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index 8ccbac7..d5d0621 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -47,6 +47,18 @@ register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end end device ref i2c2 on chip drivers/i2c/sx9324 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd Gerrit-Change-Number: 62675 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62064 ) Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Michael/Werner, can you please help to test this CL as your side as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 15:44:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm: Add smm_get_cbmemc_buffer for legacy SMI handler
by Patrick Rudolph (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Raul Rangel. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62793 ) Change subject: cpu/x86/smm: Add smm_get_cbmemc_buffer for legacy SMI handler ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba4952d2d2a984adaf8fe3508e6b82d396aa9bb Gerrit-Change-Number: 62793 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 15:41:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Subrata Banik, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Hello build bot (Jenkins), Mariusz Szafrański, Jonathan Zhang, Angel Pons, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Suresh Bellampalli, Tim Wawrzynczak, Vanessa Eusebio, Nick Vaccaro, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62064 to look at the new patch set (#7). Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code This patch moves `pmc_clear_pmcon_sts` function into common code and remove SoC specific instances, except the Apollolake. Apollolake FSP hides PMC PCI device using NotifyPhase API unlike other SoC platforms where FSP disables PMC inside FSP-S API. Hence, Apollolake case is really special and can't be redirected to IA common PMC block for `pmc_clear_pmcon_sts()` implementation. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 --- M src/soc/intel/alderlake/include/soc/pm.h M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/elkhartlake/include/soc/pm.h M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/jasperlake/include/soc/pm.h M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/include/soc/pm.h M src/soc/intel/tigerlake/pmutil.c M src/soc/intel/xeon_sp/include/soc/pm.h M src/soc/intel/xeon_sp/pmutil.c 22 files changed, 45 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62064/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Fix broken links
by Martin Roth (Code Review) 14 Mar '22

14 Mar '22

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62672 ) Change subject: Documentation: Fix broken links ...................................................................... Documentation: Fix broken links This change mostly changes links that were identified as broken by the 'website_scans' jenkins job. There were some links that seem to be up at times, but that are identified by link-checker as broken because of SSL issues. At least one other link was changed to point to archive.org so that it doesn't break at some point in the future. We should probably try to make sure that everything is archived there and point to those versions when possible. There are still lots more links to do. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Reviewed-on: https://review.coreboot.org/c/coreboot/+/62672 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M Documentation/community/code_of_conduct.md M Documentation/community/conferences.md M Documentation/contributing/coding_style.md M Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/f2a85-m.md M Documentation/mainboard/asus/p8h61-m_lx.md 7 files changed, 13 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Documentation/community/code_of_conduct.md b/Documentation/community/code_of_conduct.md index 249a575..179612c 100644 --- a/Documentation/community/code_of_conduct.md +++ b/Documentation/community/code_of_conduct.md @@ -115,4 +115,4 @@ This Code of Conduct is distributed under a [Creative Commons Attribution-ShareAlike license](http://creativecommons.org/licenses/by-sa/3.0/). It is based -on the [Citizen Code of Conduct](http://citizencodeofconduct.org/) +on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofcon… diff --git a/Documentation/community/conferences.md b/Documentation/community/conferences.md index dc4a1b9..db89f27 100644 --- a/Documentation/community/conferences.md +++ b/Documentation/community/conferences.md @@ -14,7 +14,7 @@ [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_fa… by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebo…) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03) -[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018) +[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/cong… ([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27) [coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018 diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md index e3c92af..6564545 100644 --- a/Documentation/contributing/coding_style.md +++ b/Documentation/contributing/coding_style.md @@ -966,11 +966,14 @@ The C Programming Language, Second Edition by Brian W. Kernighan and Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8 (paperback), 0-13-110370-9 (hardback). URL: -<http://cm.bell-labs.com/cm/cs/cbook/> +<https://duckduckgo.com/?q=isbn+0-13-110362-8> or +<https://www.google.com/search?q=isbn+0-13-110362-8. + The Practice of Programming by Brian W. Kernighan and Rob Pike. Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL: -<http://cm.bell-labs.com/cm/cs/tpop/> +<https://duckduckgo.com/?q=ISBN+0-201-61586-X> or +<https://www.google.com/search?q=ISBN+0-201-61586-X> GNU manuals - where in compliance with K&R and this text - for cpp, gcc, gcc internals and indent, all available from diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 4a20bb6..a4f6e57 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -131,4 +131,4 @@ [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%… [flashrom]: https://flashrom.org/Flashrom -[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf +[H110M-DVS manual]: https://web.archive.org/web/20191023230631/http://asrock.pc.cdn.bitgravity.… diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md index 6a0da5b..9d5c288 100644 --- a/Documentation/mainboard/asrock/h81m-hds.md +++ b/Documentation/mainboard/asrock/h81m-hds.md @@ -130,4 +130,4 @@ [ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/ [W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf [flashrom]: https://flashrom.org/Flashrom -[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf +[Board manual]: https://web.archive.org/web/20191231093418/http://asrock.pc.cdn.bitgravity.… diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md index dfde07f..ce7c2497 100644 --- a/Documentation/mainboard/asus/f2a85-m.md +++ b/Documentation/mainboard/asus/f2a85-m.md @@ -190,9 +190,9 @@ - [Board manual] - Flash chip datasheet [W25Q64FV] -[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/ -[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf +[ASUS F2A85-M]: https://web.archive.org/web/20160320065008/http://www.asus.com/Motherboards… +[Board manual]: https://web.archive.org/web/20211028063105/https://dlcdnets.asus.com/pub/AS… [flashrom]: https://flashrom.org/Flashrom [Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines [TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3 -[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[W25Q64FV]: https://web.archive.org/web/20220127184640/https://www.winbond.com/resource… diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md index 212ed97..a4b54cd 100644 --- a/Documentation/mainboard/asus/p8h61-m_lx.md +++ b/Documentation/mainboard/asus/p8h61-m_lx.md @@ -106,6 +106,6 @@ - [Flash chip datasheet][W25Q32BV] [ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/ -[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.p… +[W25Q32BV]: https://web.archive.org/web/20211002141814/https://www.winbond.com/resource… [flashrom]: https://flashrom.org/Flashrom [Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Gerrit-Change-Number: 62672 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Documentation: Fix broken links
by Martin Roth (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Martin Roth, Stefan Reinauer. Hello Felix Singer, build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62672 to look at the new patch set (#2). Change subject: Documentation: Fix broken links ...................................................................... Documentation: Fix broken links This change mostly changes links that were identified as broken by the 'website_scans' jenkins job. There were some links that seem to be up at times, but that are identified by link-checker as broken because of SSL issues. At least one other link was changed to point to archive.org so that it doesn't break at some point in the future. We should probably try to make sure that everything is archived there and point to those versions when possible. There are still lots more links to do. Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef --- M Documentation/community/code_of_conduct.md M Documentation/community/conferences.md M Documentation/contributing/coding_style.md M Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/asus/f2a85-m.md M Documentation/mainboard/asus/p8h61-m_lx.md 7 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62672/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef Gerrit-Change-Number: 62672 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Enable EC SMI handler
by Raul Rangel (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62599 ) Change subject: mb/google/guybrush: Enable EC SMI handler ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/guybrush/ec.c: https://review.coreboot.org/c/coreboot/+/62599/comment/95883fc8_05a0ffc1 PS2, Line 35: configure_smi(SMITYPE_ESPI_SMI, SMI_MODE_SMI); > Yeah, we could probably remove that as well if we disable the SMI handler when depthcharge starts. So one unintended side effect, is that when we boot with the lid closed, the SMI triggers, and when we initialize SMM it handles the SMI. The system seems to be in a strange state at this point. It can't seem to handle the shutdown call, so it causes a reboot. Will need to investigate more. We either need to delay setting the EC SMI mask until after SMM is setup completely, or figure out why we can't `poweroff` in early SMM. -- To view, visit https://review.coreboot.org/c/coreboot/+/62599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52b96b1b7c3c25a8355eaba4e84dbce49451b7f8 Gerrit-Change-Number: 62599 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 15:36:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush: Enable EC SMI handler
by Raul Rangel (Code Review) 14 Mar '22

14 Mar '22

1 0

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