coreboot-gerrit March 2022

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Change in coreboot[master]: MAINTAINERS: Remove myself
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62754 ) Change subject: MAINTAINERS: Remove myself ...................................................................... MAINTAINERS: Remove myself Change-Id: Ie75912698e58088ff4a334403cb331542abb40fd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62754 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M MAINTAINERS 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/MAINTAINERS b/MAINTAINERS index 07502ce..930d37e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -330,7 +330,6 @@ LENOVO MAINBOARDS M: Alexander Couzens <lynxis(a)fe80.eu> -M: Patrick Rudolph <siro(a)das-labor.org> S: Maintained F: src/mainboard/lenovo/ @@ -582,7 +581,6 @@ F: src/include/cpu/amd/ INTEL SUPPORT -M: Patrick Rudolph <siro(a)das-labor.org> S: Maintained F: src/vendorcode/intel/ F: src/cpu/intel/ -- To view, visit https://review.coreboot.org/c/coreboot/+/62754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie75912698e58088ff4a334403cb331542abb40fd Gerrit-Change-Number: 62754 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Use generic enum type values
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62708 ) Change subject: soc/intel/common: Use generic enum type values ...................................................................... soc/intel/common: Use generic enum type values The patch uses generic enum type values for EOP command handler. So, it renames cse_eop_result enum type to cse_cmd_result and also renames the enum values to have generic name. TEST=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62708 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 87da5fc..bc6d837 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -11,11 +11,11 @@ #include <timestamp.h> #include <types.h> -enum cse_eop_result { - CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED, - CSE_EOP_RESULT_SUCCESS, - CSE_EOP_RESULT_ERROR, - CSE_EOP_RESULT_DISABLED, +enum cse_cmd_result { + CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED, + CSE_CMD_RESULT_SUCCESS, + CSE_CMD_RESULT_ERROR, + CSE_CMD_RESULT_DISABLED, }; static bool cse_disable_mei_bus(void) @@ -47,7 +47,7 @@ return true; } -static enum cse_eop_result cse_send_eop(void) +static enum cse_cmd_result cse_send_eop(void) { enum { EOP_REQUESTED_ACTION_CONTINUE = 0, @@ -74,7 +74,7 @@ cse_is_hfs1_com_soft_temp_disable()) { printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT " "TEMP DISABLE state, skipping EOP\n"); - return CSE_EOP_RESULT_SUCCESS; + return CSE_CMD_RESULT_SUCCESS; } /* @@ -87,25 +87,25 @@ if (cse_is_hfs1_com_soft_temp_disable()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - return CSE_EOP_RESULT_ERROR; - return CSE_EOP_RESULT_DISABLED; + return CSE_CMD_RESULT_ERROR; + return CSE_CMD_RESULT_DISABLED; } if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); if (heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } if (resp.hdr.result) { printk(BIOS_ERR, "HECI: EOP Resp Failed: %u\n", resp.hdr.result); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } printk(BIOS_INFO, "CSE: EOP requested action: "); @@ -113,13 +113,13 @@ switch (resp.requested_actions) { case EOP_REQUESTED_ACTION_GLOBAL_RESET: printk(BIOS_INFO, "global reset\n"); - return CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED; + return CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED; case EOP_REQUESTED_ACTION_CONTINUE: printk(BIOS_INFO, "continue boot\n"); - return CSE_EOP_RESULT_SUCCESS; + return CSE_CMD_RESULT_SUCCESS; default: printk(BIOS_INFO, "unknown %u\n", resp.requested_actions); - return CSE_EOP_RESULT_ERROR; + return CSE_CMD_RESULT_ERROR; } } @@ -139,20 +139,20 @@ "Preventing system from booting into an insecure state.\n"); } -static void handle_cse_eop_result(enum cse_eop_result result) +static void handle_cse_eop_result(enum cse_cmd_result result) { switch (result) { - case CSE_EOP_RESULT_GLOBAL_RESET_REQUESTED: + case CSE_CMD_RESULT_GLOBAL_RESET_REQUESTED: printk(BIOS_INFO, "CSE requested global reset in EOP response, resetting...\n"); do_global_reset(); break; - case CSE_EOP_RESULT_SUCCESS: + case CSE_CMD_RESULT_SUCCESS: printk(BIOS_INFO, "CSE EOP successful, continuing boot\n"); break; - case CSE_EOP_RESULT_DISABLED: + case CSE_CMD_RESULT_DISABLED: printk(BIOS_INFO, "CSE is disabled, continuing boot\n"); break; - case CSE_EOP_RESULT_ERROR: /* fallthrough */ + case CSE_CMD_RESULT_ERROR: /* fallthrough */ default: printk(BIOS_ERR, "Failed to send EOP to CSE, %d\n", result); /* For vboot, trigger recovery mode if applicable, as there is 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0efa8fff08318ed863010db289959d113f4767e Gerrit-Change-Number: 62708 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Use heci_reset() in the CSE TX and RX flows
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62587 ) Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows ...................................................................... soc/intel/common: Use heci_reset() in the CSE TX and RX flows The patch implements error handling as per the ME BWG guide. The BWG recommends HECI interface reset if there is a timeout or malformed response is received from the CSE. Also, the patch triggers HECI interface reset if the CSE link state is not ready in the heci_send() API. TEST=Verify HECI Interface reset in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 810973b..bbd8afc 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -458,6 +458,8 @@ return CSE_TX_RX_SUCCESS; } + printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n"); + heci_reset(); return CSE_TX_ERR_CSE_NOT_READY; } @@ -548,7 +550,7 @@ ret = recv_one_message(&hdr, p, left, &received); if (ret) { printk(BIOS_ERR, "HECI: Failed to receive!\n"); - return ret; + goto CSE_RX_ERR_HANDLE; } left -= received; p += received; @@ -563,6 +565,9 @@ } } +CSE_RX_ERR_HANDLE: + printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n"); + heci_reset(); return CSE_RX_ERR_CSE_NOT_READY; } 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Gerrit-Change-Number: 62587 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Implement error codes for for heci_send_receive()
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62299 ) Change subject: soc/intel/common: Implement error codes for for heci_send_receive() ...................................................................... soc/intel/common: Implement error codes for for heci_send_receive() The patch implements below changes: 1. Implements different error codes and use them in appropriate failure scenarios of below functions: a. heci_send() b. recv_one_message() c. heci_receive() 2. As heci_send_receive() is updated to return appropriate error codes in different error scenarios of sending and receiving the HECI commands. As the function is updated to return 0 when success, and non-zero values in the failure scenarios, so all caller function have been updated. BUG=b:220652101 TEST=Verified CSE RX and TX APIs return error codes appropriately in the simulated error scenarios. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62299 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 5 files changed, 86 insertions(+), 47 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 7d1e6e7..0f11809 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -78,7 +78,7 @@ reply_size = sizeof(rmsg); - if (!heci_send_receive(&msg, sizeof(msg), &rmsg, &reply_size, HECI_MKHI_ADDR)) { + if (heci_send_receive(&msg, sizeof(msg), &rmsg, &reply_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: Failed to read file\n"); return 0; } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 18f9ba8..810973b 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -407,7 +407,7 @@ * Returns 1 on success and 0 otherwise. * In case of error heci_reset() may be required. */ -static int +static enum cse_tx_rx_status heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) { uint8_t retry; @@ -416,7 +416,7 @@ const uint8_t *p; if (!msg || !len) - return 0; + return CSE_TX_ERR_INPUT; clear_int(); @@ -455,40 +455,41 @@ } while (remaining > 0 && sent != 0); if (!remaining) - return 1; + return CSE_TX_RX_SUCCESS; } - return 0; + + return CSE_TX_ERR_CSE_NOT_READY; } -static size_t -recv_one_message(uint32_t *hdr, void *buff, size_t maxlen) +static enum cse_tx_rx_status +recv_one_message(uint32_t *hdr, void *buff, size_t maxlen, size_t *recv_len) { uint32_t reg, *p = buff; - size_t recv_slots, recv_len, remainder, i; + size_t recv_slots, remainder, i; /* first get the header */ if (!wait_read_slots(1)) - return 0; + return CSE_RX_ERR_TIMEOUT; *hdr = read_slot(); - recv_len = hdr_get_length(*hdr); + *recv_len = hdr_get_length(*hdr); - if (!recv_len) + if (!*recv_len) printk(BIOS_WARNING, "HECI: message is zero-sized\n"); - recv_slots = bytes_to_slots(recv_len); + recv_slots = bytes_to_slots(*recv_len); i = 0; - if (recv_len > maxlen) { + if (*recv_len > maxlen) { printk(BIOS_ERR, "HECI: response is too big\n"); - return 0; + return CSE_RX_ERR_RESP_LEN_MISMATCH; } /* wait for the rest of messages to arrive */ wait_read_slots(recv_slots); /* fetch whole slots first */ - while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) { + while (i < ALIGN_DOWN(*recv_len, SLOT_SIZE)) { *p++ = read_slot(); i += SLOT_SIZE; } @@ -498,16 +499,15 @@ * we received junk */ if (!cse_ready()) - return 0; + return CSE_RX_ERR_CSE_NOT_READY; - remainder = recv_len % SLOT_SIZE; + remainder = *recv_len % SLOT_SIZE; if (remainder) { reg = read_slot(); memcpy(p, &reg, remainder); } - - return recv_len; + return CSE_TX_RX_SUCCESS; } /* @@ -518,15 +518,16 @@ * and 1 on success. * In case of error heci_reset() may be required. */ -static int heci_receive(void *buff, size_t *maxlen) +static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen) { uint8_t retry; size_t left, received; uint32_t hdr = 0; uint8_t *p; + enum cse_tx_rx_status ret = CSE_RX_ERR_TIMEOUT; if (!buff || !maxlen || !*maxlen) - return 0; + return CSE_RX_ERR_INPUT; clear_int(); @@ -544,10 +545,10 @@ * complete or we run out of space in caller-provided buffer. */ do { - received = recv_one_message(&hdr, p, left); - if (!received) { + ret = recv_one_message(&hdr, p, left, &received); + if (ret) { printk(BIOS_ERR, "HECI: Failed to receive!\n"); - return 0; + return ret; } left -= received; p += received; @@ -558,27 +559,32 @@ if ((hdr & MEI_HDR_IS_COMPLETE) && received) { *maxlen = p - (uint8_t *) buff; - return 1; + return CSE_TX_RX_SUCCESS; } } - return 0; + + return CSE_RX_ERR_CSE_NOT_READY; } -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, - uint8_t cse_addr) +enum cse_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, + size_t *rcv_sz, uint8_t cse_addr) { - if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr)) { + enum cse_tx_rx_status ret; + + ret = heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr); + if (ret) { printk(BIOS_ERR, "HECI: send Failed\n"); - return 0; + return ret; } if (rcv_msg != NULL) { - if (!heci_receive(rcv_msg, rcv_sz)) { + ret = heci_receive(rcv_msg, rcv_sz); + if (ret) { printk(BIOS_ERR, "HECI: receive Failed\n"); - return 0; + return ret; } } - return 1; + return ret; } /* @@ -704,7 +710,7 @@ status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, HECI_MKHI_ADDR); - printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); + printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", !status ? "success" : "failure"); return status; } @@ -777,7 +783,7 @@ return 0; } - if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), + if (heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), &resp, &resp_size, HECI_MKHI_ADDR)) return 0; @@ -826,7 +832,7 @@ return -1; } - if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), + if (heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); return -1; @@ -893,7 +899,7 @@ heci_reset(); - if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, + if (heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, HECI_MKHI_ADDR)) return CB_ERR; @@ -1171,7 +1177,7 @@ } printk(BIOS_DEBUG, "HECI: ME state change send %s!\n", - send ? "success" : "failure"); + !send ? "success" : "failure"); printk(BIOS_DEBUG, "HECI: ME state change result %s!\n", result ? "success" : "failure"); diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index af6abb8..87da5fc 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -34,7 +34,7 @@ size_t reply_sz = sizeof(reply); - if (!heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR)) { + if (heci_send_receive(&msg, sizeof(msg), &reply, &reply_sz, HECI_MEI_ADDR)) { printk(BIOS_ERR, "HECI: Failed to Disable MEI bus\n"); return false; } @@ -98,7 +98,7 @@ printk(BIOS_INFO, "HECI: Sending End-of-Post\n"); - if (!heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { + if (heci_send_receive(&msg, sizeof(msg), &resp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "HECI: EOP send/receive fail\n"); return CSE_EOP_RESULT_ERROR; } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 67dae1c..2756814 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -143,7 +143,7 @@ size_t resp_size = sizeof(struct cse_boot_perf_rsp); - if (!heci_send_receive(&req, sizeof(req), boot_perf_rsp, &resp_size, + if (heci_send_receive(&req, sizeof(req), boot_perf_rsp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "cse_lite: Could not get boot performance data\n"); return false; @@ -241,7 +241,7 @@ size_t resp_size = sizeof(struct get_bp_info_rsp); - if (!heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size, + if (heci_send_receive(&info_req, sizeof(info_req), bp_info_rsp, &resp_size, HECI_MKHI_ADDR)) { printk(BIOS_ERR, "cse_lite: Could not get partition info\n"); return false; @@ -294,7 +294,7 @@ struct mkhi_hdr switch_resp; size_t sw_resp_sz = sizeof(struct mkhi_hdr); - if (!heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz, + if (heci_send_receive(&switch_req, sizeof(switch_req), &switch_resp, &sw_resp_sz, HECI_MKHI_ADDR)) return false; @@ -331,7 +331,7 @@ struct mkhi_hdr data_clr_rsp; size_t data_clr_rsp_sz = sizeof(data_clr_rsp); - if (!heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, + if (heci_send_receive(&data_clr_rq, sizeof(data_clr_rq), &data_clr_rsp, &data_clr_rsp_sz, HECI_MKHI_ADDR)) { return false; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index f94fc73..8fd8ba0 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -109,6 +109,39 @@ struct me_version fitc; } __packed; +/* CSE RX and TX error status */ +enum cse_tx_rx_status { + /* + * Transmission of HECI message is success or + * Reception of HECI message is success. + */ + CSE_TX_RX_SUCCESS = 0, + + /* Timeout to send a message to CSE */ + CSE_TX_ERR_TIMEOUT = 1, + + /* Timeout to receive the response message from CSE */ + CSE_RX_ERR_TIMEOUT = 2, + + /* + * Response length doesn't match with expected + * response message length + */ + CSE_RX_ERR_RESP_LEN_MISMATCH = 3, + + /* CSE is not ready during TX flow */ + CSE_TX_ERR_CSE_NOT_READY = 4, + + /* CSE is not ready during RX flow */ + CSE_RX_ERR_CSE_NOT_READY = 5, + + /* Invalid input arguments provided for TX API */ + CSE_TX_ERR_INPUT = 6, + + /* Invalid input arguments provided for RX API */ + CSE_RX_ERR_INPUT = 7, +}; + /* CSE recovery sub-error codes */ enum csme_failure_reason { /* No error */ @@ -300,10 +333,10 @@ * Send message from BIOS_HOST_ADDR to cse_addr. * Sends snd_msg of size snd_sz, and reads message into buffer pointed by * rcv_msg of size rcv_sz - * Returns 0 on failure and 1 on success. + * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. */ -int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, - uint8_t cse_addr); +enum cse_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, + size_t *rcv_sz, uint8_t cse_addr); /* * Attempt device reset. This is useful and perhaps only thing left to do when 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedee748ed6d81436c6b125f2eb2722be3f5f8f0 Gerrit-Change-Number: 62299 Gerrit-PatchSet: 11 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.nest(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62553 ) Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... mb/google/brya/var/kinox: update overridetree 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. BUG=b:218786363, b:214025396, b:212183045 TEST=emerge-brask coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62553 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/kinox/overridetree.cb 1 file changed, 213 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/kinox/overridetree.cb b/src/mainboard/google/brya/variants/kinox/overridetree.cb index 4f2c04a..f850d11 100644 --- a/src/mainboard/google/brya/variants/kinox/overridetree.cb +++ b/src/mainboard/google/brya/variants/kinox/overridetree.cb @@ -1,6 +1,217 @@ chip soc/intel/alderlake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + }" - device domain 0 on - end + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Rear USB Type A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB + + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + # I2C Port Config + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + device domain 0 on + device ref pcie_rp7 on + chip drivers/net + register "customized_leds" = "0x05af" + register "wake" = "GPE0_DW0_07" #GPP_A7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H22)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "device_index" = "0" + device pci 00.0 on end + end + end # RTL8111K Ethernet NIC + device ref pcie_rp8 off end + device ref pcie_rp9 off end + + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref tbt_pcie_rp2 off end # Disable TCP Port 2 + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end + + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C0 + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Hub"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Hub"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = + "ACPI_PLD_TYPE_A(UNKNOWN, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb3_port4 on end + end + end + end + end + end end 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 14 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62740 ) Change subject: mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK ...................................................................... mb/google/guybrush: Fix building with VBOOT_STARTS_IN_BOOTBLOCK The verstage.c file contains PSP verstage specific code. We don't need it when using x86 verstage. BUG=b:193050286 TEST=Build and boot guybrush with x86 verstage Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/Makefile.inc M src/mainboard/google/guybrush/verstage.c 2 files changed, 1 insertion(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc index 56ef2b3..cdfb53b 100644 --- a/src/mainboard/google/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -12,7 +12,7 @@ all-y += spi_speeds.c -verstage-y += verstage.c +verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c verstage-$(CONFIG_CHROMEOS) += chromeos.c subdirs-y += variants/baseboard diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c index 35bfa0a..f827fdd 100644 --- a/src/mainboard/google/guybrush/verstage.c +++ b/src/mainboard/google/guybrush/verstage.c @@ -13,9 +13,6 @@ const struct soc_amd_gpio *gpios, *override_gpios; size_t num_gpios, override_num_gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) - return; - gpios = variant_early_gpio_table(&num_gpios); override_gpios = variant_early_override_gpio_table(&override_num_gpios); gpio_configure_pads_with_override(gpios, num_gpios, override_gpios, override_num_gpios); @@ -27,9 +24,6 @@ size_t num_gpios; uint32_t dword; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) - return; - gpios = variant_espi_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); @@ -52,9 +46,6 @@ const struct soc_amd_gpio *gpios; size_t num_gpios; - if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) - return; - gpios = variant_tpm_gpio_table(&num_gpios); gpio_configure_pads(gpios, num_gpios); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070 Gerrit-Change-Number: 62740 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Set EPP to 45% for all Brya variants
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62655 ) Change subject: mb/google/brya: Set EPP to 45% for all Brya variants ...................................................................... mb/google/brya: Set EPP to 45% for all Brya variants This sets EPP value to be 45% for all Brya variants. Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms. BUG=b:219785001 BRANCH=firmware-brya-14505.B TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73. Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 0558307..d67fd4b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -119,6 +119,10 @@ }, }" + # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + device domain 0 on device ref igpu on end device ref dtt on end 7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02 Gerrit-Change-Number: 62655 Gerrit-PatchSet: 11 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add EPP override support
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62654 ) Change subject: soc/intel/alderlake: Add EPP override support ...................................................................... soc/intel/alderlake: Add EPP override support This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. BUG=b:219785001 BRANCH=firmware-brya-14505.B Signed-off-by: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62654 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c 2 files changed, 23 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 7a16902..e77a3dc 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -559,6 +559,10 @@ * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ uint8_t SlowSlewRate[NUM_VR_DOMAINS]; + + /* Energy-Performance Preference (HWP feature) */ + bool enable_energy_perf_pref; + uint8_t energy_perf_pref_value; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 66db16b..7d4fb9c 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -122,6 +122,11 @@ /* Set energy policy */ set_energy_perf_bias(ENERGY_POLICY_NORMAL); + const config_t *conf = config_of_soc(); + /* Set energy-performance preference */ + if (conf->enable_energy_perf_pref) + if (check_energy_perf_cap()) + set_energy_perf_pref(conf->energy_perf_pref_value); /* Enable Turbo */ enable_turbo(); } @@ -132,6 +137,19 @@ smm_relocate(); } +static void pre_mp_init(void) +{ + soc_fsp_load(); + + const config_t *conf = config_of_soc(); + if (conf->enable_energy_perf_pref) { + if (check_energy_perf_cap()) + enable_energy_perf_pref(); + else + printk(BIOS_WARNING, "Energy Performance Preference not supported!\n"); + } +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -152,7 +170,7 @@ * that are set prior to ramstage. * Real MTRRs programming are being done after resource allocation. */ - .pre_mp_init = soc_fsp_load, + .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798 Gerrit-Change-Number: 62654 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Deepika Punyamurtula <deepika.punyamurtula(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Update DPTF setting
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62729 ) Change subject: mb/google/dedede: Update DPTF setting ...................................................................... mb/google/dedede: Update DPTF setting Update PL1, PL2, and temperature sensor values from thermal team, as well as, we remove unused temperature sensors according to baseboard/devicetree.cb and mainboard schematic. After we check DTT setting, the thermal and performance test pass. BRANCH=dedede BUG=b:204229229 TEST=on beadrix, run following commands: localhost /tmp # cat /sys/class/thermal/thermal_zone*/type x86_pkg_temp INT3400 Thermal TSR0 TSR1 TCPU localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp 45000 20000 32800 32800 39000 Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Super Ni <super.ni(a)intel.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 1 file changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved Super Ni: Looks good to me, but someone else must approve Teddy Shih: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 9c6d931..7f2d62f 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -40,6 +40,46 @@ }" device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Dedede boards if not overridden + chip drivers/intel/dptf + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""CPU"" + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 80, 4000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 110, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 110, 4000), + }" + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 110, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 110, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 110, SHUTDOWN), + }" + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 4000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 250, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + register "controls.charger_perf" = "{ + [0] = { 55, 3500 }, + [1] = { 47, 3000 }, + [2] = { 39, 2500 }, + [3] = { 31, 2000 }, + }" + device generic 0 on end + end + end device pci 05.0 off end # IPU - MIPI Camera device pci 14.0 on chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/62729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3 Gerrit-Change-Number: 62729 Gerrit-PatchSet: 4 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Super Ni <super.ni(a)intel.corp-partner.google.com> Gerrit-Reviewer: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jack Cheng <jack.cheng(a)ecs.corp-partner.google.com> Gerrit-CC: Raymond Chung <raymondchung(a)ami.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62713 ) Change subject: mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2 ...................................................................... mb/googe/skyrim/baseboard/devicetree: update USB port device ID on xhci2 The one USB2 port on the XHCI2 controller should have the port ID 2.0, since it's the first USB2 port on that XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index ac9bd2be..61bc93d 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -127,7 +127,7 @@ register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_10)" - device usb 2.3 alias usb2_port5 on end + device usb 2.0 alias usb2_port5 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/62713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a370132960939bccec4eb69a6590d0880b04137 Gerrit-Change-Number: 62713 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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