coreboot-gerrit March 2022

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Change in coreboot[master]: Documentation/tutorial/part1.md: Add Fedora package `patch`
by Angel Pons (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Eloy. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62765 ) Change subject: Documentation/tutorial/part1.md: Add Fedora package `patch` ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62765/comment/d9013c1c_5fd5fdcd PS1, Line 7: Documentation/tutorial/part1.md: add patch package > ... […] Done Commit Message: https://review.coreboot.org/c/coreboot/+/62765/comment/4db24a09_32296f55 PS2, Line 8: I imagine this is needed to build crossgcc. I'd mention so in the commit message: It is necessary to build crossgcc. -- To view, visit https://review.coreboot.org/c/coreboot/+/62765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32f6507b4d8346bf94aaccd3eef4f22697c33965 Gerrit-Change-Number: 62765 Gerrit-PatchSet: 2 Gerrit-Owner: Eloy Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eloy Gerrit-Comment-Date: Mon, 14 Mar 2022 16:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/kgpe-d16/Kconfig: Bring back symbols that are already defined
by Name of user not set (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Michał Żygowski. 0xloem(a)gmail.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62187 ) Change subject: mb/asus/kgpe-d16/Kconfig: Bring back symbols that are already defined ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Hi, I've been spending a little time hacking on the KGPE-D16 changes to see if I can get my KFSN4-DRE to work too. I was asked in IRC if I had any free cycles to review these changesets. I'm completely new to both gerrit and coreboot. This is a simple organising commit that uncomments necessary Kconfig symbols for the KGPE. It LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/62187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db1f33648b1f51fea531b3e9f1bc18e9e7721e8 Gerrit-Change-Number: 62187 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: 0xloem(a)gmail.com Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 16:28:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Add support for PCI MMIO CONFIG access.
by build bot (Jenkins) (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Ravi kumar, Furquan Shaikh, Arthur Heymans, Prasad Malisetty. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57615 ) Change subject: libpayload: Add support for PCI MMIO CONFIG access. ...................................................................... Patch Set 35: Verified-1 (2 comments) File payloads/libpayload/drivers/qc_pci_mmio_ops.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143902): https://review.coreboot.org/c/coreboot/+/57615/comment/d4649a7d_9fca9af0 PS35, Line 107: cfg_address = (void*) pci_mmio_info->config_base; "(foo*)" should be "(foo *)" File payloads/libpayload/include/qc_pci.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143902): https://review.coreboot.org/c/coreboot/+/57615/comment/658995f0_710b10b5 PS35, Line 70: #endif trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/57615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Gerrit-Change-Number: 57615 Gerrit-PatchSet: 35 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 16:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
by Tim Wawrzynczak (Code Review) 14 Mar '22

14 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62703 ) Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage ...................................................................... mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage Currently the BayHub eMMC enable pin is using the default configuration from the baseboard, which leads to RTD3 not being able to control the GPIO when exiting and entering suspend. To fix this, program the GPIO in the ramstage GPIO table. BUG=b:222436260 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage scope enable pin while performing suspend stress and enable pin works as expected. test suspend stress 1000 cycles passed on primus. Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/gpio.c M src/mainboard/google/brya/variants/primus4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index d4d6684..c224866 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -49,6 +49,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), diff --git a/src/mainboard/google/brya/variants/primus4es/gpio.c b/src/mainboard/google/brya/variants/primus4es/gpio.c index d2dadc3..5947b6e 100644 --- a/src/mainboard/google/brya/variants/primus4es/gpio.c +++ b/src/mainboard/google/brya/variants/primus4es/gpio.c @@ -53,6 +53,8 @@ PAD_NC(GPP_E3, NONE), /* E7 : PROC_GP1 ==> NC */ PAD_NC(GPP_E7, NONE), + /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ + PAD_CFG_GPO(GPP_E20, 1, DEEP), /* E21 : DDP2_CTRLDATA ==> NC */ PAD_NC(GPP_E21, NONE), 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Gerrit-Change-Number: 62703 Gerrit-PatchSet: 9 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
by Tim Wawrzynczak (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Sean Rhodes, Jeremy Soller, Paul Menzel, Nick Vaccaro, Michael Niewöhner, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62766 ) Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008 Gerrit-Change-Number: 62766 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 16:13:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl/chip.h: Convert all camel case variables to snake case
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Maulik V Vaghela, 9elements QA, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62645 ) Change subject: soc/intel/adl/chip.h: Convert all camel case variables to snake case ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: this patch needs to be rebased -- To view, visit https://review.coreboot.org/c/coreboot/+/62645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0 Gerrit-Change-Number: 62645 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 15:59:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/starlabs/labtop: Pull SSD Pin to low when entering S3
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62636 ) Change subject: mb/starlabs/labtop: Pull SSD Pin to low when entering S3 ...................................................................... mb/starlabs/labtop: Pull SSD Pin to low when entering S3 Pull GPP_D16 to low when suspending, otherwise it will remain active and use power. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/starlabs/labtop/acpi/sleep.asl 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl index 7ed74e3..78a2d29 100644 --- a/src/mainboard/starlabs/labtop/acpi/sleep.asl +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -2,6 +2,12 @@ Method (MPTS, 1, NotSerialized) { +#if CONFIG(BOARD_STARLABS_STARBOOK_TGL) + If (Arg0 == 0x03) { + \_SB.PCI0.CTXS (GPP_D16) + } +#endif + RPTS (Arg0) } 13 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1 Gerrit-Change-Number: 62636 Gerrit-PatchSet: 15 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/common/block: Add APL and GLK PCI IDs for HDA
by Felix Singer (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Sean Rhodes, Patrick Rudolph. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61804 ) Change subject: intel/common/block: Add APL and GLK PCI IDs for HDA ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37df388a93ffc06e716085a58d0d00ed5c6fa9e9 Gerrit-Change-Number: 61804 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 15:54:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62698 ) Change subject: mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes ...................................................................... mb/siemens/mc_ehl: Increase SPD buffer size to 512 bytes DDR4 SPD data needs to be 512 byte to comply with the spec. Though there is no vital timing data used beyond 256 byte there are some part information which will be used to show the part info in the coreboot log. If the buffer is too small this log shows garbage. This patch increases the SPD buffer size from 256 byte to 512 to avoid side effects. Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index 82e2090..21b33bd 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -14,7 +14,7 @@ { static struct spd_info spd_info; const struct mb_cfg *board_cfg = variant_memcfg_config(); - static uint8_t spd_data[0x100]; + static uint8_t spd_data[CONFIG_DIMM_SPD_SIZE]; const char *cbfs_hwi_name = "hwinfo.hex"; /* Initialize SPD information for LPDDR4x from HW-Info primarily with a fallback to @@ -24,7 +24,7 @@ (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; - spd_info.spd_spec.spd_data_ptr_info.spd_data_len = sizeof(spd_data); + spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; } else { printk(BIOS_WARNING, "SPD in HW-Info not valid, fall back to spd.bin!\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/62698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c Gerrit-Change-Number: 62698 Gerrit-PatchSet: 5 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/starlabs/labtop: Remove unused return value from MWAK
by Felix Held (Code Review) 14 Mar '22

14 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62420 ) Change subject: mb/starlabs/labtop: Remove unused return value from MWAK ...................................................................... mb/starlabs/labtop: Remove unused return value from MWAK Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I00f8ea86a7e03a0b1bf9e68f75582a2ae70aef02 --- M src/mainboard/starlabs/labtop/acpi/sleep.asl 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/starlabs/labtop/acpi/sleep.asl b/src/mainboard/starlabs/labtop/acpi/sleep.asl index 9dc818d0..867d804 100644 --- a/src/mainboard/starlabs/labtop/acpi/sleep.asl +++ b/src/mainboard/starlabs/labtop/acpi/sleep.asl @@ -11,5 +11,4 @@ Method (MWAK, 1, NotSerialized) { RWAK (Arg0) - Return (0x00) } 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f8ea86a7e03a0b1bf9e68f75582a2ae70aef02 Gerrit-Change-Number: 62420 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022