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Hello build bot (Jenkins), Wonkyu Kim, Subrata Banik, Ravishankar Sarawadi, Tim Wawrzynczak, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
soc/intel/common: Add IOE P2SB for TCSS
Meteor Lake has the IOE Die for TCSS. This change adds the IOE P2SB
sideband access and exposes API for TCSS usage.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I01f551b6e1f50ebdc1cef2ceee815a492030db19
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/p2sb.h
M src/soc/intel/common/block/p2sb/Kconfig
M src/soc/intel/common/block/p2sb/Makefile.inc
A src/soc/intel/common/block/p2sb/ioe_p2sb.c
M src/soc/intel/common/block/p2sb/p2sb.c
5 files changed, 74 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/62721/6
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Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62743 )
Change subject: mb/google/herobrine: consolidate hoglin/herobrine QUP inits
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> Hi Qualcomm, […]
hi shelly.
I have applied mentioned patch and verified on hoglin(CRD3.1) hardware.. device able to boot..
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Change subject: mb/google/brask/variants/moli: set eMMC pin in bootblock
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62770/comment/f8d647a3_dfb8316d
PS3, Line 9: 1.add eMMC enable pin in bootblock
: 2.set eMMC reset pin unable in bootblock
suggestion:
```
1. Assert eMMC enable pin in bootblock
2. Deassert eMMC reset pin in bootblock
```
Also should reset be deasserted after power enable? in other words, should the controller be powered on with reset asserted (in reset)?
https://review.coreboot.org/c/coreboot/+/62770/comment/9520dc41_3bbb44e8
PS3, Line 12:
nit: remove extra blank line
File src/mainboard/google/brya/variants/moli/gpio.c:
https://review.coreboot.org/c/coreboot/+/62770/comment/665c78d8_6ec1ef4a
PS3, Line 73: /* B3 : PROC_GP2 ==> EMMC_PERST_L */
: PAD_CFG_GPO(GPP_B3, 0, DEEP),
:
Please keep line 75 and 73 together, the comment goes with the pad programming
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Change subject: util/ifdtool: Add Meteor Lake platform support under IFDv2
......................................................................
Patch Set 5: Code-Review+2
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Change subject: libpayload: Parse DDR Information using coreboot tables
......................................................................
Patch Set 38:
(2 comments)
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/59193/comment/f44a8839_2e23bec4
PS37, Line 263: _INFO
> CBMEM_ID_MEM_CHIP_INFO was added in a previous patch, so I'd suggest we add "_info" consistently (fi […]
hi julius,
can you please suggest me, can i ignore this comment as already merged.
File src/commonlib/bsd/include/commonlib/bsd/mem_chip.h:
https://review.coreboot.org/c/coreboot/+/59193/comment/e3700a72_c3946639
PS37, Line 7: MEM_CHIP_DDR3 = 1,
> nit: do we maybe wanna make this a little more organized? e.g. something like […]
Done
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Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59193
to look at the new patch set (#39).
Change subject: libpayload: Parse DDR Information using coreboot tables
......................................................................
libpayload: Parse DDR Information using coreboot tables
BUG=b:182963902,b:177917361
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
---
M payloads/libpayload/include/libpayload.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
A src/commonlib/bsd/include/commonlib/bsd/mem_chip.h
4 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/39
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