coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/herobrine: consolidate hoglin/herobrine QUP inits
by Shelley Chen (Code Review) 14 Mar '22

14 Mar '22

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62743 ) Change subject: mb/google/herobrine: consolidate hoglin/herobrine QUP inits ...................................................................... mb/google/herobrine: consolidate hoglin/herobrine QUP inits Hoglin and Herobrine (proto1) should share majority of GPIOs. Conslidating the QUP initializations in mainboard. Also, putting fingerprint init in a conditional as not all devices will have an FP sensor. BUG=b:182963902,b:223826899 BRANCH=None TEST=booted BIOS on hoglin and check for i2c errors in dmesg Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c Signed-off-by: Shelley Chen <shchen(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/herobrine/mainboard.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c index 34e5d4a..7bdede0 100644 --- a/src/mainboard/google/herobrine/mainboard.c +++ b/src/mainboard/google/herobrine/mainboard.c @@ -77,8 +77,7 @@ qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* Fingerprint SPI */ qupv3_se_fw_load_and_init(QUPV3_1_SE3, SE_PROTOCOL_SPI, MIXED); - } else if (CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN) || - CONFIG(BOARD_GOOGLE_HOGLIN)) { + } else if (CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN)) { /* APPS I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE1, SE_PROTOCOL_I2C, GSI); /* ESIM SPI */ @@ -93,7 +92,8 @@ /* Audio I2C */ qupv3_se_fw_load_and_init(QUPV3_0_SE2, SE_PROTOCOL_I2C, MIXED); /* Fingerprint SPI */ - qupv3_se_fw_load_and_init(QUPV3_1_SE1, SE_PROTOCOL_SPI, MIXED); + if (CONFIG(HEROBRINE_HAS_FINGERPRINT)) + qupv3_se_fw_load_and_init(QUPV3_1_SE1, SE_PROTOCOL_SPI, MIXED); } /* Take FPMCU out of reset. Power was already applied -- To view, visit https://review.coreboot.org/c/coreboot/+/62743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c Gerrit-Change-Number: 62743 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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Change in coreboot[master]: x86/smbios_defaults: Set default system manufacturer for ChromeOS dev...
by Matt DeVillier (Code Review) 14 Mar '22

14 Mar '22

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62796 ) Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices ...................................................................... x86/smbios_defaults: Set default system manufacturer for ChromeOS devices Currently, many Linux drivers use DMI quirks to identify ChromeOS devices and handle them accordingly: namely they look for the SMBIOS system manufactuer to be "GOOGLE" or "Google", and the bios-vendor to be coreboot. Historically this was consistently the case, but recent model ChromeOS devices allow the OEM to set the mainboard manufacturer, which is also the default system manufacturer. This breaks many DMI quirks, notably ones used by SOF (sound open firmware) for audio. To fix this, set the default system manufactuer for ChromeOS devices to "Google" conditional on CONFIG_MAINBOARD_HAS_CHROMEOS, leaving the OEM customization in place for the mainboard manufacturer. Test: build/boot google/bloog with Linux 5.16, verify SOF drivers correctly detect device as a Chromebook and load the appropriate audio firmware. Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/arch/x86/smbios_defaults.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/62796/1 diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c index 8b62ebb..5f1731c 100644 --- a/src/arch/x86/smbios_defaults.c +++ b/src/arch/x86/smbios_defaults.c @@ -115,7 +115,10 @@ __weak const char *smbios_system_manufacturer(void) { - return smbios_mainboard_manufacturer(); + if (CONFIG(MAINBOARD_HAS_CHROMEOS)) + return "Google"; + else + return smbios_mainboard_manufacturer(); } __weak const char *smbios_system_product_name(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/62796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Gerrit-Change-Number: 62796 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage
by 9elements QA (Code Review) 14 Mar '22

14 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62703 ) Change subject: mb/google/brya/var/primus{4es}: add eMMC enable pin in ramstage ...................................................................... Patch Set 9: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95531 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/95530 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/95529 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/95528 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/95527 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95526 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/95525 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/95524 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/95523 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/95522 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/95521 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/95520 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d Gerrit-Change-Number: 62703 Gerrit-PatchSet: 9 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 22:16:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util: Add amdfwread utility
by Robert Zieba (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Robert Zieba. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62795 to look at the new patch set (#2). Change subject: util: Add amdfwread utility ...................................................................... util: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly read the soft fuse bits Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 --- A util/amdfwread/Makefile A util/amdfwread/amdfwread.c A util/amdfwread/description.md 3 files changed, 366 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/62795/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Gerrit-Change-Number: 62795 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util: Add amdfwread utility
by build bot (Jenkins) (Code Review) 14 Mar '22

14 Mar '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62795 ) Change subject: util: Add amdfwread utility ...................................................................... Patch Set 1: (3 comments) File util/amdfwread/amdfwread.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143929): https://review.coreboot.org/c/coreboot/+/62795/comment/189ed88d_e4c81dd8 PS1, Line 268: void print_usage() Bad function definition - void print_usage() should probably be void print_usage(void) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143929): https://review.coreboot.org/c/coreboot/+/62795/comment/0b0dbfba_9d99ea16 PS1, Line 315: for (size_t i = 0; i < sizeof(fw_header_offsets) / sizeof(fw_header_offsets[0]); i++) { Prefer ARRAY_SIZE(fw_header_offsets) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143929): https://review.coreboot.org/c/coreboot/+/62795/comment/0f320840_6509dae0 PS1, Line 334: } adding a line without newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/62795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Gerrit-Change-Number: 62795 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 22:06:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util: Add amdfwread utility
by Robert Zieba (Code Review) 14 Mar '22

14 Mar '22

Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62795 ) Change subject: util: Add amdfwread utility ...................................................................... util: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly read the soft fuse bits Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 --- A util/amdfwread/Makefile A util/amdfwread/amdfwread.c A util/amdfwread/description.md 3 files changed, 365 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/62795/1 diff --git a/util/amdfwread/Makefile b/util/amdfwread/Makefile new file mode 100644 index 0000000..8cab478 --- /dev/null +++ b/util/amdfwread/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: BSD-3-Clause + +HOSTCC ?= cc + +SRC = amdfwread.c +OBJ = $(SRC:%.c=%.o) +TARGET = amdfwread +WERROR=-Werror -Wno-unused-function +CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR} + +all: $(TARGET) + +$(TARGET): $(OBJ) + $(CC) $(OBJ) $(LDFLAGS) -o $@ + +%.o: %.c $(HEADER) + $(CC) $(CFLAGS) -c -o $@ $< + +clean: + @rm -f $(TARGET) $(OBJ) + +distclean: clean + +help: + @echo "${TARGET}: Create AMD Firmware combination" + @echo "Targets: all, clean, distclean, help" + @echo "To disable warnings as errors, run make as:" + @echo " make all WERROR=\"\"" + +.PHONY: all clean distclean help diff --git a/util/amdfwread/amdfwread.c b/util/amdfwread/amdfwread.c new file mode 100644 index 0000000..055065b --- /dev/null +++ b/util/amdfwread/amdfwread.c @@ -0,0 +1,334 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <getopt.h> +#include <stddef.h> +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <unistd.h> + +#define ERR(...) fprintf(stderr, __VA_ARGS__) + +/* Structs and enums taken from amdfwtool */ +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + AMD_DEBUG_UNLOCK = 0x13, + AMD_HW_IPCFG = 0x20, + AMD_WRAPPED_IKEK = 0x21, + AMD_TOKEN_UNLOCK = 0x22, + AMD_SEC_GASKET = 0x24, + AMD_MP2_FW = 0x25, + AMD_DRIVER_ENTRIES = 0x28, + AMD_FW_KVM_IMAGE = 0x29, + AMD_S0I3_DRIVER = 0x2d, + AMD_ABL0 = 0x30, + AMD_ABL1 = 0x31, + AMD_ABL2 = 0x32, + AMD_ABL3 = 0x33, + AMD_ABL4 = 0x34, + AMD_ABL5 = 0x35, + AMD_ABL6 = 0x36, + AMD_ABL7 = 0x37, + AMD_FW_PSP_WHITELIST = 0x3a, + AMD_VBIOS_BTLOADER = 0x3c, + AMD_FW_L2_PTR = 0x40, + AMD_FW_USB_PHY = 0x44, + AMD_FW_TOS_SEC_POLICY = 0x45, + AMD_FW_DRTM_TA = 0x47, + AMD_FW_RECOVERYAB_A = 0x48, + AMD_FW_RECOVERYAB_B = 0x4A, + AMD_FW_BIOS_TABLE = 0x49, + AMD_FW_KEYDB_BL = 0x50, + AMD_FW_KEYDB_TOS = 0x51, + AMD_FW_PSP_VERSTAGE = 0x52, + AMD_FW_VERSTAGE_SIG = 0x53, + AMD_RPMC_NVRAM = 0x54, + AMD_FW_SPL = 0x55, + AMD_FW_DMCU_ERAM = 0x58, + AMD_FW_DMCU_ISR = 0x59, + AMD_FW_PSP_BOOTLOADER_AB = 0x73, + AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ + AMD_FW_GEC, + AMD_FW_XHCI, + AMD_FW_INVALID, /* Real last one to detect the last entry in table. */ + AMD_FW_SKIP /* This is for non-applicable options. */ +} amd_fw_type; + +struct second_gen_efs { /* todo: expand for Server products */ + int gen:1; /* Client products only use bit 0 */ + int reserved:31; +} __attribute__((packed)); + +typedef struct _embedded_firmware { + uint32_t signature; /* 0x55aa55aa */ + uint32_t imc_entry; + uint32_t gec_entry; + uint32_t xhci_entry; + uint32_t psp_directory; + union { + uint32_t new_psp_directory; + uint32_t combo_psp_directory; + }; + uint32_t bios0_entry; /* todo: add way to select correct entry */ + uint32_t bios1_entry; + uint32_t bios2_entry; + struct second_gen_efs efs_gen; + uint32_t bios3_entry; + uint32_t reserved_2Ch; + uint32_t promontory_fw_ptr; + uint32_t lp_promontory_fw_ptr; + uint32_t reserved_38h; + uint32_t reserved_3Ch; + uint8_t spi_readmode_f15_mod_60_6f; + uint8_t fast_speed_new_f15_mod_60_6f; + uint8_t reserved_42h; + uint8_t spi_readmode_f17_mod_00_2f; + uint8_t spi_fastspeed_f17_mod_00_2f; + uint8_t qpr_dummy_cycle_f17_mod_00_2f; + uint8_t reserved_46h; + uint8_t spi_readmode_f17_mod_30_3f; + uint8_t spi_fastspeed_f17_mod_30_3f; + uint8_t micron_detect_f17_mod_30_3f; + uint8_t reserved_4Ah; + uint8_t reserved_4Bh; + uint32_t reserved_4Ch; +} __attribute__((packed, aligned(16))) embedded_firmware; + +typedef struct _psp_directory_header { + uint32_t cookie; + uint32_t checksum; + uint32_t num_entries; + union { + uint32_t additional_info; + struct { + uint32_t dir_size:10; + uint32_t spi_block_size:4; + uint32_t base_addr:15; + uint32_t address_mode:2; + uint32_t not_used:1; + } __attribute__((packed)) additional_info_fields; + }; +} __attribute__((packed, aligned(16))) psp_directory_header; + +typedef struct _psp_directory_entry { + uint8_t type; + uint8_t subprog; + uint16_t rsvd; + uint32_t size; + uint64_t addr:62; /* or a value in some cases */ + uint64_t address_mode:2; +} __attribute__((packed)) psp_directory_entry; + +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; + uint8_t subprog; + int level; + uint64_t other; +} amd_fw_entry; + +#define EMBEDDED_FW_SIGNATURE 0x55aa55aa +#define PSP_COOKIE 0x50535024 /* 'PSP$' */ +#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ + +/* Possible locations for the header */ +const uint32_t fw_header_offsets[] = { + 0xfa0000, + 0xe20000, + 0xc20000, + 0x820000, + 0x020000, +}; + +int read_fw_header(FILE *fw, uint32_t offset, embedded_firmware *fw_header) +{ + if (fseek(fw, offset, SEEK_SET) != 0) { + ERR("Failed to seek to fw header offset 0x%x\n", offset); + return 1; + } + + if (fread(fw_header, sizeof(embedded_firmware), 1, fw) != 1) { + ERR("Failed to read fw header at 0x%x\n", offset); + return 1; + } + + return fw_header->signature != EMBEDDED_FW_SIGNATURE; +} + +int read_psp_directory(FILE *fw, uint32_t offset, uint32_t expected_cookie, + psp_directory_entry **entries, size_t *num_entries) +{ + /* Ensure the offset is relative to the file start instead of a direct + memory address. */ + offset &= 0xFFFFFF; + if (fseek(fw, offset, SEEK_SET) != 0) { + ERR("Failed to seek to PSP header at 0x%x\n", offset); + return 1; + } + + psp_directory_header header; + if (fread(&header, sizeof(psp_directory_header), 1, fw) != 1) { + ERR("Failed to read PSP header cookie\n"); + return 1; + } + + /* Ensure that we have a PSP directory. */ + if (header.cookie != expected_cookie) { + ERR("Invalid PSP header cookie value found: 0x%x, expected: 0x%x\n", + expected_cookie, header.cookie); + return 1; + } + + /* Read the entries. */ + *num_entries = header.num_entries; + *entries = malloc(sizeof(psp_directory_entry) * header.num_entries); + if (fread(*entries, sizeof(psp_directory_entry), header.num_entries, fw) + != header.num_entries) { + ERR("Failed to read %d PSP entries\n", header.num_entries); + return 1; + } + + return 0; +} + +int read_soft_fuse(FILE *fw, const embedded_firmware *fw_header) +{ + psp_directory_entry *current_entries = NULL; + size_t num_current_entries = 0; + + uint32_t psp_offset = 0; + /* 0xffffffff indicates that the offset is in new_psp_directory. */ + if (fw_header->psp_directory != 0xffffffff) + psp_offset = fw_header->psp_directory; + else + psp_offset = fw_header->new_psp_directory; + + if (read_psp_directory(fw, psp_offset, PSP_COOKIE, &current_entries, + &num_current_entries) != 0) + return 1; + + while (1) { + uint32_t l2_dir_offset = 0; + + for (size_t i = 0; i < num_current_entries; i++) { + uint32_t type = current_entries[i].type; + if (type == AMD_PSP_FUSE_CHAIN) { + amd_fw_entry *entry = (amd_fw_entry *)&current_entries[i]; + printf("Soft-fuse:0x%lX\n", entry->other); + } else if (type == AMD_FW_L2_PTR) { + /* There's a second level PSP directory to read. */ + if (l2_dir_offset != 0) + return 1; + + l2_dir_offset = current_entries[i].addr; + } + } + + free(current_entries); + + /* Didn't find an L2 PSP directory so we can stop. */ + if (l2_dir_offset == 0) + break; + + /* Read the L2 PSP directory. */ + if (read_psp_directory(fw, l2_dir_offset, PSPL2_COOKIE, &current_entries, + &num_current_entries) != 0) + return 1; + } + + return 0; +} + +enum { + AMDFW_OPT_HELP = 'h', + + /* When bit 31 is set, options are a bitfield of info to print from the + firmware image. */ + AMDFW_OPT_SOFT_FUSE = 0xF0000001, +}; + +static char const optstring[] = {AMDFW_OPT_HELP}; + +static struct option long_options[] = { + {"help", no_argument, 0, AMDFW_OPT_HELP}, + {"soft-fuse", no_argument, 0, AMDFW_OPT_SOFT_FUSE}, +}; + +void print_usage() +{ + printf("amdfwread: Examine AMD firmware images\n"); + printf("Usage: amdfwread [options] <file>\n"); + printf("--soft-fuse Print soft fuse value\n"); +} + +int main(int argc, char **argv) +{ + char *fw_file = NULL; + + int selected_functions = 0; + int index = 0; + while (1) { + int opt = getopt_long(argc, argv, optstring, long_options, &index); + + if (opt == -1) { + index++; + if (index >= argc) + return 1; + + fw_file = argv[index]; + break; + } + + if (opt == AMDFW_OPT_HELP) { + print_usage(); + return 0; + } + + selected_functions |= opt; + } + + if (selected_functions == 0) { + print_usage(); + return 0; + } + + FILE *fw = fopen(fw_file, "rb"); + if (!fw) { + ERR("Failed to open FW file %s\n", fw_file); + return 1; + } + + /* Find the FW header by checking each possible location */ + embedded_firmware fw_header; + int found_header = 0; + for (size_t i = 0; i < sizeof(fw_header_offsets) / sizeof(fw_header_offsets[0]); i++) { + if (read_fw_header(fw, fw_header_offsets[i], &fw_header) == 0) { + found_header = 1; + break; + } + } + + if (!found_header) { + ERR("Failed to find FW header\n"); + return 1; + } + + if (selected_functions & AMDFW_OPT_SOFT_FUSE) { + if (read_soft_fuse(fw, &fw_header) != 0) + return 1; + } + + fclose(fw); + return 0; +} \ No newline at end of file diff --git a/util/amdfwread/description.md b/util/amdfwread/description.md new file mode 100644 index 0000000..8d2b55d --- /dev/null +++ b/util/amdfwread/description.md @@ -0,0 +1 @@ +Read information from AMD Firmware combination `C` -- To view, visit https://review.coreboot.org/c/coreboot/+/62795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Gerrit-Change-Number: 62795 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/trogdor: Add variant Gelarshie
by Julius Werner (Code Review) 14 Mar '22

14 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62642 ) Change subject: mb/google/trogdor: Add variant Gelarshie ...................................................................... mb/google/trogdor: Add variant Gelarshie New board introduced to trogdor family. BUG=b:223101874 BRANCH=none TEST=make Signed-off-by: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62642 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M Documentation/security/vboot/list_vboot.md M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/Kconfig.name 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md index 75d20ee..8300aa8 100644 --- a/Documentation/security/vboot/list_vboot.md +++ b/Documentation/security/vboot/list_vboot.md @@ -206,6 +206,7 @@ - Stout (Lenovo Thinkpad X131e Chromebook) - Bubs - Coachz +- Gelarshie - Homestar - Kingoftown - Lazor diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index e70bc69..29b0395 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -73,6 +73,7 @@ config MAINBOARD_PART_NUMBER default "Bubs" if BOARD_GOOGLE_BUBS default "Coachz" if BOARD_GOOGLE_COACHZ + default "Gelarshie" if BOARD_GOOGLE_GELARSHIE default "Homestar" if BOARD_GOOGLE_HOMESTAR default "Kingoftown" if BOARD_GOOGLE_KINGOFTOWN default "Lazor" if BOARD_GOOGLE_LAZOR diff --git a/src/mainboard/google/trogdor/Kconfig.name b/src/mainboard/google/trogdor/Kconfig.name index f5bd7ad..db4cff0 100644 --- a/src/mainboard/google/trogdor/Kconfig.name +++ b/src/mainboard/google/trogdor/Kconfig.name @@ -10,6 +10,10 @@ bool "-> Coachz" select BOARD_GOOGLE_TROGDOR_COMMON +config BOARD_GOOGLE_GELARSHIE + bool "-> Gelarshie" + select BOARD_GOOGLE_TROGDOR_COMMON + config BOARD_GOOGLE_HOMESTAR bool "-> Homestar" select BOARD_GOOGLE_TROGDOR_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/62642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9 Gerrit-Change-Number: 62642 Gerrit-PatchSet: 8 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/trogdor: Add variant Gelarshie
by Julius Werner (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Douglas Anderson, Paul Menzel, Bob Moragues, Mars Chen. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62642 ) Change subject: mb/google/trogdor: Add variant Gelarshie ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83df3c753d0863841430fe62805250ef8efeae9 Gerrit-Change-Number: 62642 Gerrit-PatchSet: 7 Gerrit-Owner: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Douglas Anderson <dianders(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Mars Chen <chenxiangrui(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 22:04:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/herobrine: consolidate hoglin/herobrine QUP inits
by Julius Werner (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Shelley Chen, mturney mturney, Sudheer Amrabadi. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62743 ) Change subject: mb/google/herobrine: consolidate hoglin/herobrine QUP inits ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c Gerrit-Change-Number: 62743 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Comment-Date: Mon, 14 Mar 2022 21:46:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add companion device name to WWAN PCIe generic device
by Cliff Huang (Code Review) 14 Mar '22

14 Mar '22

Attention is currently required from: Bora Guvendik, Selma Bensaid, Tim Wawrzynczak, Nick Vaccaro. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62330 ) Change subject: mb/google/brya: Add companion device name to WWAN PCIe generic device ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62330/comment/46a25949_774d04c3 PS10, Line 213: rp6_wwan > Is there additional work needed for this CL? If not, can we resolve this comment so that this CL ca […] The recent merged changes for dmaProperty create _DSD, while the changes in this code review and https://review.coreboot.org/c/coreboot/+/62301 are use PCIe generic to create _DSD. This needs to be resolved. -- To view, visit https://review.coreboot.org/c/coreboot/+/62330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Gerrit-Change-Number: 62330 Gerrit-PatchSet: 10 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Mon, 14 Mar 2022 21:24:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022