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Change subject: mb/google/brya: set GPP_D0 to GPO
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/google/brya: set GPP_D0 to GPO
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/gpio.c:
https://review.coreboot.org/c/coreboot/+/62739/comment/33947c55_c6ddc40e
PS4, Line 121: PAD_CFG_GPO
> Oh yes flash_fp_mcu is setting the MODE bits to OUTPUT, so it needs to be set explicitly here
Updated.
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Hello build bot (Jenkins), YH Lin, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Zhuohao Lee, EricR Lai, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: set GPP_D0 to GPO
......................................................................
mb/google/brya: set GPP_D0 to GPO
Based on the schematic carbine_adl-p_dvt_20211104.pdf, the GPP_D0 is
directly connected to FP module, Set GPP_D0 to GPO, DUT can flash FP
firmware successfully.
BUG=b:222188263, b:223906569
TEST=USE="project_gimble emerge-brya coreboot" and run the Fingerprint
Firmware Test.
Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com>
Change-Id: I164ffff6bd3b4058d6e28247eb7c3ed46d3891b5
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/62739/6
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Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/variants/moli: set eMMC pin in bootblock
......................................................................
mb/google/brask/variants/moli: set eMMC pin in bootblock
1.Assert eMMC enable pin in bootblock
2.Deassert eMMC reset pin unable in bootblock
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: I924fcdadaae8ed29b50369a55bad00983cf6ba19
---
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Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Looking at the Jenkins results: https://qa.coreboot. […]
By default, jenkins builds the default config with chromeos enabled and disabled. Any additional configs need to be added to the coreboot/configs folder.
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Change subject: $(TOP)/Makefile.inc: Handle the folder common before specific one
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62750/comment/f792a35d_b5eef055
PS3, Line 13: The duplicated "common" in the result string can be eliminated finally.
You say this but I don't see where you're doing it? AFAIK there's no automatic deduplication in evaluate_subdirs yet.
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Change subject: soc/intel/common: Add IOE P2SB for TCSS
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Patchset:
PS7:
Looks in the good shape.
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Change subject: mb/google/brya: Remove mainboard.asl
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/mainboard.c:
https://review.coreboot.org/c/coreboot/+/62779/comment/78827543_1442321c
PS3, Line 115: acpigen_write_if_lequal_op_int(ARG0_OP, 1);
: if (CONFIG(HAVE_SLP_S0_GATE))
: acpigen_soc_clear_tx_gpio(GPIO_SLP_S0_GATE);
: variant_generate_s0ix_hook(S0IX_ENTRY);
: acpigen_write_else();
: if (CONFIG(HAVE_SLP_S0_GATE))
: acpigen_soc_set_tx_gpio(GPIO_SLP_S0_GATE);
: variant_generate_s0ix_hook(S0IX_EXIT);
: acpigen_write_if_end();
> suggestion (adding {} only) […]
Done
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Change subject: soc/intel/common/block/p2sb: Refactor P2SB to add comprehend future SoC
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
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Patch Set 9:
(1 comment)
File src/soc/intel/common/block/pmc/pmclib.c:
https://review.coreboot.org/c/coreboot/+/62064/comment/42d8739b_e7f6695f
PS9, Line 634: && (GEN_PMCON_A <= 0xff)
hmm, nice idea but feels more like a "hack", doesn't it? Since APL is the only exception, why not have `&& ! CONFIG(SOC_INTEL_APOLLOLAKE)`? Not that nice in common code but maybe a bit better. .... or introduce a Kconfig SOC_INTEL_MEM_MAPPED_GEN_PMCON_A (yeah I know... you wanted to avoid that :) )
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