coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62791 to look at the new patch set (#4). Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... soc/mediatek: Add chip config for setting PCIe config Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c A src/soc/mediatek/mt8195/chip.h M src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/include/soc/soc_chip.h M src/soc/mediatek/mt8195/pcie.c 6 files changed, 77 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62791/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 4 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Yu-Ping Wu (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... Patch Set 15: (1 comment) File src/mainboard/google/cherry/variants/dojo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62360/comment/59aa1082_218d5210 PS15, Line 6: Remove extra indent. -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 06:10:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Remove global variable
by Yu-Ping Wu (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62800 ) Change subject: soc/mediatek: PCI: Remove global variable ...................................................................... Patch Set 1: (2 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62800/comment/83f7cd5f_b28fa190 PS1, Line 100: { Let's cache 'base' (using static variable) inside this function. https://review.coreboot.org/c/coreboot/+/62800/comment/8e739e7a_ffa55e7e PS1, Line 210: ctrl conf -- To view, visit https://review.coreboot.org/c/coreboot/+/62800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Gerrit-Change-Number: 62800 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 06:08:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Yu-Ping Wu (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62791 ) Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... Patch Set 3: (3 comments) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62791/comment/de6c25f8_a00f959b PS2, Line 109: pcie_ctrl > I add an individual patch to replace this global variable: […] Thanks. the pcidev_path_on_root approach is even better. File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62791/comment/136ba1ad_13edfa10 PS3, Line 168: ctrl "conf" or something similar https://review.coreboot.org/c/coreboot/+/62791/comment/fc96f856_1d600a94 PS3, Line 180: ctrl Same. -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 06:07:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62791 ) Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62791/comment/e52d3caa_a5ffac92 PS2, Line 109: pcie_ctrl > I think it's ok to use PCIE_REG_BASE. […] I add an individual patch to replace this global variable: https://review.coreboot.org/c/coreboot/+/62800/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 05:59:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62791 ) Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62791/comment/317fb033_022fff34 PS2, Line 7: setting PCIe controller data > PCIe config Done File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62791/comment/ee524ea6_0ff2f1e4 PS2, Line 168: struct > const Done https://review.coreboot.org/c/coreboot/+/62791/comment/aadd9a19_86080e5d PS2, Line 170: (struct mtk_pcie_controller *) > Why do we need to cast? Removed https://review.coreboot.org/c/coreboot/+/62791/comment/fb5b36c5_53115011 PS2, Line 182: struct mtk_pcie_controller *ctrl; : uintptr_t table; : : ctrl = (struct mtk_pcie_controller *)&config->pcie_controller; > Same. Done https://review.coreboot.org/c/coreboot/+/62791/comment/7ffd476b_a3078568 PS2, Line 208: (struct mtk_pcie_controller *) > No need. Done File src/soc/mediatek/mt8195/chip.h: https://review.coreboot.org/c/coreboot/+/62791/comment/269d3668_00759ac1 PS2, Line 9: controller > config Done https://review.coreboot.org/c/coreboot/+/62791/comment/cc0988be_f6876cdf PS2, Line 9: controller > config or conf Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 05:54:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Remove global variable
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin. Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62800 ) Change subject: soc/mediatek: PCI: Remove global variable ...................................................................... soc/mediatek: PCI: Remove global variable Remove global variable and use 'pcidev_path_on_root()' to get the base address of PCIe controller. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 --- M src/soc/mediatek/common/pcie.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62800/1 diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c2299a0..490ade2 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -65,8 +65,6 @@ #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) -static const struct mtk_pcie_config *pcie_ctrl; - /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ static const char *const ltssm_str[] = { "detect.quiet", /* 0x00 */ @@ -98,17 +96,29 @@ "hotreset", /* 0x1A */ }; +static uintptr_t mtk_pcie_get_controller_base(pci_devfn_t devfn) +{ + struct device *root_dev = pcidev_path_on_root(devfn); + const mtk_soc_config_t *config = config_of(root_dev); + + return config->pcie_config.base; +} + volatile union pci_bank *pci_map_bus(pci_devfn_t dev) { u32 val, devfn, bus; + static uintptr_t base = 0; + + if (!base) + base = mtk_pcie_get_controller_base(dev); devfn = PCI_DEV2DEVFN(dev); bus = PCI_DEV2SEGBUS(dev); val = PCIE_CFG_HEADER(bus, devfn); - write32p(pcie_ctrl->base + PCIE_CFGNUM_REG, val); + write32p(base + PCIE_CFGNUM_REG, val); - return (void *)(pcie_ctrl->base + PCIE_CFG_OFFSET_ADDR); + return (void *)(base + PCIE_CFG_OFFSET_ADDR); } static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, @@ -197,35 +207,34 @@ void mtk_pcie_domain_enable(struct device *dev) { const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *ctrl = &config->pcie_config; const char *ltssm_state; size_t tries = 0; uint32_t val; - pcie_ctrl = &config->pcie_config; - /* Set as RC mode */ - val = read32p(pcie_ctrl->base + PCIE_SETTING_REG); + val = read32p(ctrl->base + PCIE_SETTING_REG); val |= PCIE_RC_MODE; - write32p(pcie_ctrl->base + PCIE_SETTING_REG, val); + write32p(ctrl->base + PCIE_SETTING_REG, val); /* Set class code */ - val = read32p(pcie_ctrl->base + PCIE_PCI_IDS_1); + val = read32p(ctrl->base + PCIE_PCI_IDS_1); val &= ~GENMASK(31, 8); val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(pcie_ctrl->base + PCIE_PCI_IDS_1, val); + write32p(ctrl->base + PCIE_PCI_IDS_1, val); /* Mask all INTx interrupts */ - val = read32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG); + val = read32p(ctrl->base + PCIE_INT_ENABLE_REG); val &= ~PCIE_INTX_ENABLE; - write32p(pcie_ctrl->base + PCIE_INT_ENABLE_REG, val); + write32p(ctrl->base + PCIE_INT_ENABLE_REG, val); /* De-assert reset signals */ - mtk_pcie_reset(pcie_ctrl->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(ctrl->base + PCIE_RST_CTRL_REG, false); if (!retry(100, - (tries++, read32p(pcie_ctrl->base + PCIE_LINK_STATUS_REG) & + (tries++, read32p(ctrl->base + PCIE_LINK_STATUS_REG) & PCIE_CTRL_LINKUP), mdelay(1))) { - val = read32p(pcie_ctrl->base + PCIE_LTSSM_STATUS_REG); + val = read32p(ctrl->base + PCIE_LTSSM_STATUS_REG); ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/62800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Gerrit-Change-Number: 62800 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62360 to look at the new patch set (#15). Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... mb/google/cherry: Add PCIe domain support Add override device tree for dojo and add PCIe domain support. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 --- M src/mainboard/google/cherry/Kconfig A src/mainboard/google/cherry/variants/dojo/overridetree.cb 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add chip config for setting PCIe config
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62791 to look at the new patch set (#3). Change subject: soc/mediatek: Add chip config for setting PCIe config ...................................................................... soc/mediatek: Add chip config for setting PCIe config Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c A src/soc/mediatek/mt8195/chip.h M src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/include/soc/soc_chip.h M src/soc/mediatek/mt8195/pcie.c 6 files changed, 75 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62791/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Gerrit-Change-Number: 62791 Gerrit-PatchSet: 3 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: x86/smbios_defaults: Set default system manufacturer for ChromeOS dev...
by Paul Menzel (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Martin Roth, Matt DeVillier, Tim Wawrzynczak. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62796 ) Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62796/comment/5979645f_37855171 PS1, Line 14: This breaks many DMI quirks, notably ones used by SOF (sound : open firmware) for audio. Do you know of the Chromium OS Linux kernel commit making this work for Chromium OS? https://review.coreboot.org/c/coreboot/+/62796/comment/554bf137_03b1ad1a PS1, Line 9: Currently, many Linux drivers use DMI quirks to identify ChromeOS devices and : handle them accordingly: namely they look for the SMBIOS system manufactuer : to be "GOOGLE" or "Google", and the bios-vendor to be coreboot. Historically : this was consistently the case, but recent model ChromeOS devices allow the : OEM to set the mainboard manufacturer, which is also the default system : manufacturer. This breaks many DMI quirks, notably ones used by SOF (sound : open firmware) for audio. Please reflow for 72 characters per line. File src/arch/x86/smbios_defaults.c: https://review.coreboot.org/c/coreboot/+/62796/comment/b26d4657_a55f9bae PS1, Line 121: return smbios_mainboard_manufacturer(); You could you the ternary operator, use the if statement, and also add a log message, that it’s overwritten. -- To view, visit https://review.coreboot.org/c/coreboot/+/62796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Gerrit-Change-Number: 62796 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 05:49:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022