coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Arthur Heymans (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Damien Zammit, Edward O'Callaghan, Angel Pons. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... Patch Set 2: (1 comment) File src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62759/comment/49d133ee_741c8085 PS2, Line 18: 0xa00 That decode address does not seem to be set up in genX_dec. There is no real reason to override it, so I'd just remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/device.c: remove warning for missing apic read resources
by Yu-Ping Wu (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Martin Roth. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/12471 ) Change subject: device/device.c: remove warning for missing apic read resources ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/12471/comment/6554f647_2adbe489 PS2, Line 9: We have had the "APIC: 00 missing read_resources" messages > I found this devicetree in google/corsola. Looking at the soc code, I couldn't […] You're right. It doesn't do anything. I uploaded CB:62805 to remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/12471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c Gerrit-Change-Number: 12471 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Myles Watson <mylesgw(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:46:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Rex-BC Chen, Paul Menzel, Angel Pons. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 17: (1 comment) File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62359/comment/aa90823d_404b6848 PS16, Line 16: bootblock-$(CONFIG_PCI) += pcie.c > move below bootblock-y += ../common/tracker.c ../common/tracker_v2. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 17 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:45:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Jianjun Wang (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62359 to look at the new patch set (#17). Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... soc/mediatek: PCI: Assert PERST# at bootblock stage Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and wait for 100ms, assert the pin in bootblock stage so that the extra 100ms delay could be avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 17 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google: Remove unused cpu device
by Yu-Ping Wu (Code Review) 15 Mar '22

15 Mar '22

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62805 ) Change subject: mb/google: Remove unused cpu device ...................................................................... mb/google: Remove unused cpu device The cpu device listed in MediaTek platforms' devicetree.cb doesn't actually do anything, except causing an error during device initialization: CPU: 00 missing read_resources Therefore, remove it from the devicetree. BUG=b:224419346 TEST=emerge-corsola coreboot TEST=Krabby booted up successfully BRANCH=none Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/mainboard/google/asurada/devicetree.cb M src/mainboard/google/cherry/devicetree.cb M src/mainboard/google/corsola/devicetree.cb M src/mainboard/google/kukui/devicetree.cb M src/mainboard/google/oak/devicetree.cb 5 files changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62805/1 diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb index 0bdeec2..91ff9ce 100644 --- a/src/mainboard/google/asurada/devicetree.cb +++ b/src/mainboard/google/asurada/devicetree.cb @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8192 - device cpu_cluster 0 on - device cpu 0 on end - end + device cpu_cluster 0 on end end diff --git a/src/mainboard/google/cherry/devicetree.cb b/src/mainboard/google/cherry/devicetree.cb index 17fccc2..c16350c 100644 --- a/src/mainboard/google/cherry/devicetree.cb +++ b/src/mainboard/google/cherry/devicetree.cb @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8195 - device cpu_cluster 0 on - device cpu 0 on end - end + device cpu_cluster 0 on end end diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 0c4bcb5..0e8bb91 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8186 - device cpu_cluster 0 on - device cpu 0 on end - end + device cpu_cluster 0 on end end diff --git a/src/mainboard/google/kukui/devicetree.cb b/src/mainboard/google/kukui/devicetree.cb index 8efab95..45f2aad 100644 --- a/src/mainboard/google/kukui/devicetree.cb +++ b/src/mainboard/google/kukui/devicetree.cb @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8183 - device cpu_cluster 0 on - device cpu 0 on end - end + device cpu_cluster 0 on end end diff --git a/src/mainboard/google/oak/devicetree.cb b/src/mainboard/google/oak/devicetree.cb index f021ab2..c11a901 100644 --- a/src/mainboard/google/oak/devicetree.cb +++ b/src/mainboard/google/oak/devicetree.cb @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only chip soc/mediatek/mt8173 - device cpu_cluster 0 on - device cpu 0 on end - end + device cpu_cluster 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/62805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf9f7cf65da6a0dd0a0e1f556d5772573ba3e930 Gerrit-Change-Number: 62805 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brask/variants/moli: update gpio for moli
by Raihow Shi (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62802 to look at the new patch set (#3). Change subject: mb/google/brask/variants/moli: update gpio for moli ...................................................................... mb/google/brask/variants/moli: update gpio for moli Update the GPIO configuration of moli BUG=b:220821454 Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Ia54256244111a99cb130b74f78c37815099a021a --- M src/mainboard/google/brya/variants/moli/gpio.c 1 file changed, 8 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/62802/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia54256244111a99cb130b74f78c37815099a021a Gerrit-Change-Number: 62802 Gerrit-PatchSet: 3 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Felix Singer (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Damien Zammit, Edward O'Callaghan, Angel Pons. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62759/comment/92e229f5_8cb5489a PS2, Line 11: The code in this commit is untested as I reworked his port into a variant. Please do a separate commit to turn it into a variant. Patchset: PS2: > All resolved. Do we need to test on the CMT before merging? I don't have the hw myself. […] Yes, it should be tested. -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:40:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Damien Zammit Gerrit-MessageType: comment

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Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Damien Zammit (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Edward O'Callaghan, Angel Pons. Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Adding you as a reviewer 😎 -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:39:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Add mic mute switch setting
by Frank Wu (Code Review) 15 Mar '22

15 Mar '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62804 ) Change subject: mb/google/brya/var/banshee: Add mic mute switch setting ...................................................................... mb/google/brya/var/banshee: Add mic mute switch setting Using the GPP_F22 as mic mute switch in banshee. BUG=b:223737606, b:216110896 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d --- M src/mainboard/google/brya/variants/banshee/gpio.c M src/mainboard/google/brya/variants/banshee/overridetree.cb 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62804/1 diff --git a/src/mainboard/google/brya/variants/banshee/gpio.c b/src/mainboard/google/brya/variants/banshee/gpio.c index 9bf6518..7af92e7 100644 --- a/src/mainboard/google/brya/variants/banshee/gpio.c +++ b/src/mainboard/google/brya/variants/banshee/gpio.c @@ -186,7 +186,8 @@ PAD_NC(GPP_F20, NONE), /* F21 : EXT_PWR_GATE2# ==> NC */ PAD_NC(GPP_F21, NONE), - /* F22 : NC */ + /* F22 : NC ==> MIC_SW */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_F22, NONE, DEEP), /* F23 : NC */ /* H0 : GPPH0_BOOT_STRAP1 */ diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 08550d2..033de61 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -194,6 +194,17 @@ register "property_list[0].integer" = "1" device i2c 1a on end end + chip drivers/generic/gpio_keys + register "name" = ""MUTE"" + register "label" = ""mic_mute_switch"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F22)" + register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED" + register "key.dev_name" = ""MMSW"" + register "key.linux_code" = "SW_MUTE_DEVICE" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""mic_mute_switch_key"" + device generic 0 on end + end end #I2C0 device ref i2c1 on chip drivers/i2c/tpm -- To view, visit https://review.coreboot.org/c/coreboot/+/62804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d Gerrit-Change-Number: 62804 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Rex-BC Chen (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Jianjun Wang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 16: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/3ee84456_ba723870 PS1, Line 13: delay. > Here is the prototype (src/soc/mediatek/mt8195/pcie.c line 86): […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 07:29:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022