coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/var/volmar: Disable thunderbolt
by Ren Kuo (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62810 to look at the new patch set (#2). Change subject: mb/google/brya/var/volmar: Disable thunderbolt ...................................................................... mb/google/brya/var/volmar: Disable thunderbolt Disable thunderbolot(TBT) pcie for volmar. It had been disabled for volmar fit image. Refer to chrome-internal:4459289 BUG=b:223319313 TEST=Build and run on DUT. Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/volmar/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62810/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Gerrit-Change-Number: 62810 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: 3rdparty/amd_blobs: advance submodule pointer
by Jason Glenesk (Code Review) 15 Mar '22

15 Mar '22

Jason Glenesk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62811 ) Change subject: 3rdparty/amd_blobs: advance submodule pointer ...................................................................... 3rdparty/amd_blobs: advance submodule pointer This adds the following commits: * a069321 cezanne: Update SMU firmware to 64.62.0 * d8a51cb cezanne: Upgrade ABL to 0x22146070 Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/62811/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 9e8f457..a069321 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 9e8f457edcc359552a5d0113568a2d1670009178 +Subproject commit a0693217d2fea9f3c05f6d96008c1ad301ed69e6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I066252eda56b8b62db420cbcfc95c97875a3b6d1 Gerrit-Change-Number: 62811 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: hp/z220_cmt_workstation: Add variant of z220_sff_workstation
by Damien Zammit (Code Review) 15 Mar '22

15 Mar '22

Damien Zammit has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62759 ) Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ...................................................................... Abandoned See CB:62808 and CB:62809 -- To view, visit https://review.coreboot.org/c/coreboot/+/62759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Gerrit-Change-Number: 62759 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya/var/volmar: Disable thunderbolt
by Ren Kuo (Code Review) 15 Mar '22

15 Mar '22

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62810 ) Change subject: mb/google/brya/var/volmar: Disable thunderbolt ...................................................................... mb/google/brya/var/volmar: Disable thunderbolt Disable thunderbolot(TBT) pcie for volmar. It had been disabled for volmar fit image. Refer to chrome-internal:4459289 BUG=b:223319313 TEST=Build and boot into eMMC storage Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/volmar/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/62810/1 diff --git a/src/mainboard/google/brya/variants/volmar/overridetree.cb b/src/mainboard/google/brya/variants/volmar/overridetree.cb index f54753b..8d3815a 100644 --- a/src/mainboard/google/brya/variants/volmar/overridetree.cb +++ b/src/mainboard/google/brya/variants/volmar/overridetree.cb @@ -85,6 +85,10 @@ device domain 0 on device ref dtt on + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" -- To view, visit https://review.coreboot.org/c/coreboot/+/62810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e Gerrit-Change-Number: 62810 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: hp/z220_series: Add Z220 CMT Workstation variant
by Damien Zammit (Code Review) 15 Mar '22

15 Mar '22

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62809 ) Change subject: hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... hp/z220_series: Add Z220 CMT Workstation variant This is based on previous work done by a good friend of mine. This commit needs to be boot tested on a Z220 CMT Workstation, (but I suspect it works). Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/z220_series/Kconfig M src/mainboard/hp/z220_series/Kconfig.name A src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c A src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb 4 files changed, 200 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/62809/1 diff --git a/src/mainboard/hp/z220_series/Kconfig b/src/mainboard/hp/z220_series/Kconfig index bb1093b..7a1b59a 100644 --- a/src/mainboard/hp/z220_series/Kconfig +++ b/src/mainboard/hp/z220_series/Kconfig @@ -41,9 +41,11 @@ config VARIANT_DIR default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION config MAINBOARD_PART_NUMBER default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/hp/z220_series/Kconfig.name b/src/mainboard/hp/z220_series/Kconfig.name index 77b36ad..c1d0396 100644 --- a/src/mainboard/hp/z220_series/Kconfig.name +++ b/src/mainboard/hp/z220_series/Kconfig.name @@ -1,3 +1,7 @@ config BOARD_HP_Z220_SFF_WORKSTATION bool "Z220 SFF Workstation" select BOARD_HP_Z220_SERIES + +config BOARD_HP_Z220_CMT_WORKSTATION + bool "Z220 CMT Workstation" + select BOARD_HP_Z220_SERIES diff --git a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c new file mode 100644 index 0000000..fb80217 --- /dev/null +++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/gpio.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb new file mode 100644 index 0000000..c787b50 --- /dev/null +++ b/src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x103c 0x1791 inherit + + chip southbridge/intel/bd82x6x + + register "sata_port_map" = "0x3f" + + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.5 on end # PCIe Port #6 + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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Change in coreboot[master]: hp/z220_series: Convert z220_sff_workstation into variant
by Damien Zammit (Code Review) 15 Mar '22

15 Mar '22

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62808 ) Change subject: hp/z220_series: Convert z220_sff_workstation into variant ...................................................................... hp/z220_series: Convert z220_sff_workstation into variant No functional change, just refactoring to make room for CMT variant. $ diff static.c ~/static.c.orig $ Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- R src/mainboard/hp/z220_series/Kconfig R src/mainboard/hp/z220_series/Kconfig.name A src/mainboard/hp/z220_series/Makefile.inc R src/mainboard/hp/z220_series/acpi/ec.asl R src/mainboard/hp/z220_series/acpi/platform.asl R src/mainboard/hp/z220_series/acpi/superio.asl R src/mainboard/hp/z220_series/board_info.txt R src/mainboard/hp/z220_series/cmos.default R src/mainboard/hp/z220_series/cmos.layout R src/mainboard/hp/z220_series/data.vbt R src/mainboard/hp/z220_series/devicetree.cb R src/mainboard/hp/z220_series/dsdt.asl R src/mainboard/hp/z220_series/early_init.c R src/mainboard/hp/z220_series/gma-mainboard.ads R src/mainboard/hp/z220_series/hda_verb.c R src/mainboard/hp/z220_series/mainboard.c R src/mainboard/hp/z220_series/variants/z220_sff_workstation/gpio.c A src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb D src/mainboard/hp/z220_sff_workstation/Makefile.inc 19 files changed, 33 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/62808/1 diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_series/Kconfig similarity index 69% rename from src/mainboard/hp/z220_sff_workstation/Kconfig rename to src/mainboard/hp/z220_series/Kconfig index d706665..bb1093b 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_series/Kconfig @@ -1,7 +1,6 @@ -if BOARD_HP_Z220_SFF_WORKSTATION +config BOARD_HP_Z220_SERIES + def_bool n -config BOARD_SPECIFIC_OPTIONS - def_bool y select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,6 +19,8 @@ select GFX_GMA_ANALOG_I2C_HDMI_B select MAINBOARD_USES_IFD_GBE_REGION +if BOARD_HP_Z220_SERIES + config VBOOT select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT @@ -36,10 +37,19 @@ default 0x570000 config MAINBOARD_DIR - default "hp/z220_sff_workstation" + default "hp/z220_series" + +config VARIANT_DIR + default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION config MAINBOARD_PART_NUMBER - default "HP Z220 SFF Workstation" + default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(MAINBOARDDIR)/data.vbt" config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig.name b/src/mainboard/hp/z220_series/Kconfig.name similarity index 69% rename from src/mainboard/hp/z220_sff_workstation/Kconfig.name rename to src/mainboard/hp/z220_series/Kconfig.name index 037ebc0..77b36ad 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig.name +++ b/src/mainboard/hp/z220_series/Kconfig.name @@ -1,2 +1,3 @@ config BOARD_HP_Z220_SFF_WORKSTATION bool "Z220 SFF Workstation" + select BOARD_HP_Z220_SERIES diff --git a/src/mainboard/hp/z220_series/Makefile.inc b/src/mainboard/hp/z220_series/Makefile.inc new file mode 100644 index 0000000..00426a8 --- /dev/null +++ b/src/mainboard/hp/z220_series/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/ec.asl b/src/mainboard/hp/z220_series/acpi/ec.asl similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/acpi/ec.asl rename to src/mainboard/hp/z220_series/acpi/ec.asl diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl b/src/mainboard/hp/z220_series/acpi/platform.asl similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/acpi/platform.asl rename to src/mainboard/hp/z220_series/acpi/platform.asl diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl b/src/mainboard/hp/z220_series/acpi/superio.asl similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/acpi/superio.asl rename to src/mainboard/hp/z220_series/acpi/superio.asl diff --git a/src/mainboard/hp/z220_sff_workstation/board_info.txt b/src/mainboard/hp/z220_series/board_info.txt similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/board_info.txt rename to src/mainboard/hp/z220_series/board_info.txt diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.default b/src/mainboard/hp/z220_series/cmos.default similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/cmos.default rename to src/mainboard/hp/z220_series/cmos.default diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_series/cmos.layout similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/cmos.layout rename to src/mainboard/hp/z220_series/cmos.layout diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_series/data.vbt similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/data.vbt rename to src/mainboard/hp/z220_series/data.vbt Binary files differ diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb similarity index 98% rename from src/mainboard/hp/z220_sff_workstation/devicetree.cb rename to src/mainboard/hp/z220_series/devicetree.cb index 0de9cfa..4611bec 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -30,7 +30,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_series/dsdt.asl similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/dsdt.asl rename to src/mainboard/hp/z220_series/dsdt.asl diff --git a/src/mainboard/hp/z220_sff_workstation/early_init.c b/src/mainboard/hp/z220_series/early_init.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/early_init.c rename to src/mainboard/hp/z220_series/early_init.c diff --git a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads b/src/mainboard/hp/z220_series/gma-mainboard.ads similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads rename to src/mainboard/hp/z220_series/gma-mainboard.ads diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_series/hda_verb.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/hda_verb.c rename to src/mainboard/hp/z220_series/hda_verb.c diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_series/mainboard.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/mainboard.c rename to src/mainboard/hp/z220_series/mainboard.c diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_series/variants/z220_sff_workstation/gpio.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/gpio.c rename to src/mainboard/hp/z220_series/variants/z220_sff_workstation/gpio.c diff --git a/src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb new file mode 100644 index 0000000..c31bf33 --- /dev/null +++ b/src/mainboard/hp/z220_series/variants/z220_sff_workstation/overridetree.cb @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x103c 0x1791 inherit + + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0xf" + device pci 1c.4 on end # dummy setting + end + end +end diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc deleted file mode 100644 index f0b34f9..0000000 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -bootblock-y += gpio.c -romstage-y += gpio.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/62808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Gerrit-Change-Number: 62808 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage
by Rex-BC Chen (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage ...................................................................... Patch Set 17: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/81aefc4c_bb0766ab PS9, Line 14: 100ms > Can we use a SRAM to store the timestamp? […] we just need to use 8 bytes to store this information (uint64_t) -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 17 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 08:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Update DPTF parameters for Banshee
by Eric Lai (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Sumeet R Pawnikar, Ricky Chang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62807 ) Change subject: mb/google/brya/var/banshee: Update DPTF parameters for Banshee ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 Gerrit-Change-Number: 62807 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ricky Chang <rickytlchang(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ricky Chang <rickytlchang(a)google.com> Gerrit-Comment-Date: Tue, 15 Mar 2022 08:42:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: x86/smbios_defaults: Set default system manufacturer for ChromeOS dev...
by Felix Singer (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Martin Roth, Matt DeVillier, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62796 ) Change subject: x86/smbios_defaults: Set default system manufacturer for ChromeOS devices ...................................................................... Patch Set 1: (1 comment) File src/arch/x86/smbios_defaults.c: https://review.coreboot.org/c/coreboot/+/62796/comment/6e0ba03f_73886a17 PS1, Line 119: return "Google"; I would like to avoid vendor specific configurations in common code. In my opinion, This should be done in vendorcode/google/chromeos. -- To view, visit https://review.coreboot.org/c/coreboot/+/62796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9de17fa12689ab4e627b995818aa3d2653102b04 Gerrit-Change-Number: 62796 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 08:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/banshee: Update DPTF parameters for Banshee
by Frank Wu (Code Review) 15 Mar '22

15 Mar '22

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62807 ) Change subject: mb/google/brya/var/banshee: Update DPTF parameters for Banshee ...................................................................... mb/google/brya/var/banshee: Update DPTF parameters for Banshee Follow thermal team design to update thermal table. BUG=b:223492897 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 --- M src/mainboard/google/brya/variants/banshee/overridetree.cb 1 file changed, 28 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/62807/1 diff --git a/src/mainboard/google/brya/variants/banshee/overridetree.cb b/src/mainboard/google/brya/variants/banshee/overridetree.cb index 08550d2..1c9e0f1 100644 --- a/src/mainboard/google/brya/variants/banshee/overridetree.cb +++ b/src/mainboard/google/brya/variants/banshee/overridetree.cb @@ -50,6 +50,8 @@ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + register "tcc_offset" = "10" # TCC of 90 + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -64,21 +66,21 @@ [0] = { .target = DPTF_CPU, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 50), - TEMP_PCT(65, 30), + TEMP_PCT(57, 78), + TEMP_PCT(54, 70), + TEMP_PCT(51, 60), + TEMP_PCT(48, 50), + TEMP_PCT(44, 37), } }, [1] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(50, 90), - TEMP_PCT(48, 70), - TEMP_PCT(46, 60), - TEMP_PCT(43, 40), - TEMP_PCT(40, 30), + TEMP_PCT(55, 78), + TEMP_PCT(52, 70), + TEMP_PCT(49, 60), + TEMP_PCT(46, 50), + TEMP_PCT(43, 37), } } }" @@ -86,33 +88,33 @@ ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [0] = DPTF_CRITICAL(CPU, 127, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 15000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, + .min_power = 5000, + .max_power = 30000, + .time_window_min = 30 * MSECS_PER_SEC, + .time_window_max = 30 * MSECS_PER_SEC, + .granularity = 100, }, .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, + .min_power = 60000, + .max_power = 60000, + .time_window_min = 32 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000, + .granularity = 500, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/62807 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88 Gerrit-Change-Number: 62807 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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